diff --git a/Plx/Plx.pro b/Plx/Plx.pro
index 9aab6b0..4a49cbc 100755
--- a/Plx/Plx.pro
+++ b/Plx/Plx.pro
@@ -32,12 +32,12 @@ unix {
 
 
 
-unix:!macx: LIBS += -L$$PWD/../../Plxlibrary/Library/ -lPlxApi
+unix:!macx: LIBS += -L$$PWD/../Plxlibrary/Library/ -lPlxApi
 
-INCLUDEPATH += $$PWD/../../Plxlibrary/Library
-DEPENDPATH += $$PWD/../../Plxlibrary/Library
+INCLUDEPATH += $$PWD/../Plxlibrary/Library
+DEPENDPATH += $$PWD/../Plxlibrary/Library
 
-INCLUDEPATH += $$PWD/../../Plxlibrary
-DEPENDPATH += $$PWD/../../Plxlibrary
+INCLUDEPATH += $$PWD/../Plxlibrary
+DEPENDPATH += $$PWD/../Plxlibrary
 
-unix:!macx: PRE_TARGETDEPS += $$PWD/../../Plxlibrary/Library/libPlxApi.a
+unix:!macx: PRE_TARGETDEPS += $$PWD/../Plxlibrary/Library/libPlxApi.a
diff --git a/Plx/include/LowLevel/Exception/HonaAlreadyStartedException.h b/Plx/include/LowLevel/Exception/HonaAlreadyStartedException.h
index 65ad341..a704414 100755
--- a/Plx/include/LowLevel/Exception/HonaAlreadyStartedException.h
+++ b/Plx/include/LowLevel/Exception/HonaAlreadyStartedException.h
@@ -15,7 +15,7 @@ public:
 
     virtual const char* what() const throw()
     {
-        return "";
+        return "AlreadyStarted";
     }
 };
 
diff --git a/Plx/include/LowLevel/HonaLowLevelAPI.h b/Plx/include/LowLevel/HonaLowLevelAPI.h
index 43f2523..4af4350 100755
--- a/Plx/include/LowLevel/HonaLowLevelAPI.h
+++ b/Plx/include/LowLevel/HonaLowLevelAPI.h
@@ -3,7 +3,6 @@
 #include <QObject>
 #include <QMutex>
 #include <QWaitCondition>
-#include <QTimer>
 
 #include "LowLevel/Setting/Setting.h"
 #include "LowLevel/HonaPacket.h"
@@ -74,9 +73,11 @@ private:
     HonaPacket tempHonaPacketIntS;
     HonaPacket tempHonaPacketResS;
 
-public:
     quint64 toaStartBoard = 0;
 
+public:
+
+
     HonaLowLevelAPI(QObject* parent = nullptr);
     ~HonaLowLevelAPI()
     {
@@ -119,7 +120,6 @@ private:
 
 public:
 
-
 signals:
     void lowLevelHonaData(QList<HonaPacket> honaPacketList, quint32 hsruLoss, quint32 Doa);
 
diff --git a/Plx/include/LowLevel/HonaPacket.h b/Plx/include/LowLevel/HonaPacket.h
index 1d73c3e..3fb0574 100755
--- a/Plx/include/LowLevel/HonaPacket.h
+++ b/Plx/include/LowLevel/HonaPacket.h
@@ -10,7 +10,7 @@
 class HonaPacket
 {
 private:
-    qreal toaClock;
+    qreal toaClock = 1.0e7;
     honaPacketType m_PacketType;
     quint32 m_PacketNumber;
     quint64 m_Toa;
diff --git a/Plx/src/LowLevel/HonaLowLevelAPI.cpp b/Plx/src/LowLevel/HonaLowLevelAPI.cpp
index 2f7cdd2..f2f742d 100755
--- a/Plx/src/LowLevel/HonaLowLevelAPI.cpp
+++ b/Plx/src/LowLevel/HonaLowLevelAPI.cpp
@@ -2,8 +2,9 @@
 #include <include/LowLevel/Utils/Utils.h>
 #include "include/LowLevel/HonaLowLevelAPI.h"
 #include "include/Wrapper/PlxWrapper.h"
+
 #include <QDebug>
-#include <QDateTime>
+#include <QTimer>
 
 quint32 HonaLowLevelAPI::packetLenInt4;
 quint32 HonaLowLevelAPI::packetLenRes4;
@@ -25,6 +26,7 @@ quint32 HonaLowLevelAPI::nextIntS;
 
 #define PLX_ID 0x9054
 
+
 /*************************************************************************************************/
 HonaLowLevelAPI::HonaLowLevelAPI(QObject* parent) : QObject(parent)
 {
@@ -35,6 +37,24 @@ HonaLowLevelAPI::HonaLowLevelAPI(QObject* parent) : QObject(parent)
     packetLenRes123C = 6;
     packetLenIntS = 7;
     packetLenResS = 7;
+
+    nextInt4 = 0;
+    nextRes4 = 0;
+    nextSinglePulse = 0;
+    nextResS = 0;
+    nextInt123C = 0;
+    nextRes123C = 0;
+    nextIntS = 0;
+
+    tempHonaPacketInt4 = HonaPacket();
+    tempHonaPacketRes4 = HonaPacket();
+    tempHonaPacketSinglePulse = HonaPacket();
+    tempHonaPacketInt123C = HonaPacket();
+    tempHonaPacketRes123C = HonaPacket();
+    tempHonaPacketIntS = HonaPacket();
+    tempHonaPacketResS = HonaPacket();
+
+
 }
 
 /*************************************************************************************************/
@@ -42,6 +62,9 @@ void HonaLowLevelAPI::deviceReset()
 {
     if(!plxWrapper.deviceReset())
         throw HonaException();
+
+    static const int64_t TICKS_1970 = 621355968000000000ll;
+    toaStartBoard = QDateTime::currentMSecsSinceEpoch() * 10000 + TICKS_1970;
 }
 
 /*************************************************************************************************/
@@ -158,7 +181,7 @@ void HonaLowLevelAPI::writeSettingToRegisters(HonaSettings& settings)
     /************************************************************************/
 
     honaRegisterBuffer.insert(0,(honaRegisterBuffer.at(0) +
-                                 (settings.hiruSettings.threshold & 0x00000FFF)));
+        (settings.hiruSettings.threshold & 0x00000FFF)));
 
     honaRegisterBuffer.insert(1, settings.hsruSettings.honaInt123CTHR);
     honaRegisterBuffer.insert(2, settings.hsruSettings.honaRes123CTHR);
@@ -225,16 +248,14 @@ void HonaLowLevelAPI::hsruReadThread()
             throw HonaException();
         }
 
-        _hsruLoss += hsruParserInt123C(hsruReadHonaBuffer(honaReceivers::int123C),
-                                       honaPacketList);
-        _hsruLoss += hsruParserRes123C(hsruReadHonaBuffer(honaReceivers::res123C),
-                                       honaPacketList);
+        _hsruLoss += hsruParserInt123C(hsruReadHonaBuffer(honaReceivers::int123C), honaPacketList);
+        _hsruLoss += hsruParserRes123C(hsruReadHonaBuffer(honaReceivers::res123C), honaPacketList);
         _hsruLoss += hsruParserIntS(hsruReadHonaBuffer(honaReceivers::intS), honaPacketList);
         _hsruLoss += hsruParserResS(hsruReadHonaBuffer(honaReceivers::resS), honaPacketList);
         _hsruLoss += hsruParserInt4(hsruReadHonaBuffer(honaReceivers::int4), honaPacketList);
         _hsruLoss += hsruParserRes4(hsruReadHonaBuffer(honaReceivers::res4), honaPacketList);
-        _hsruLoss += hsruParserSinglePulse(hsruReadHonaBuffer(honaReceivers::singlePulse),
-                                           honaPacketList);
+        _hsruLoss += hsruParserSinglePulse(hsruReadHonaBuffer(honaReceivers::singlePulse),honaPacketList);
+
         if(!plxWrapper.deviceClosePCIChannel())
         {
             throw HonaException();
@@ -243,6 +264,7 @@ void HonaLowLevelAPI::hsruReadThread()
         {
             throw HonaException();
         }
+        QThread::usleep(200000);
         _mutex.lock();
         _hsruReadDone.wakeAll();
         _hsruUpdateAck.wait(&_mutex);
@@ -263,9 +285,6 @@ void HonaLowLevelAPI::hsruUpdateThread()
         quint32 Doa = 0;
         Doa = hiruGetDOA();
         emit lowLevelHonaData(honaPacketList, _hsruLoss, Doa);
-        QThread::msleep(200);
-        //        QDateTime time = QDateTime :: currentDateTime ();//Get the current time of the system
-        //        QString str = time.toString ("yyyy-MM-dd hh: mm: ss: zzz ddd");//Set the display format
         _hsruUpdateAck.wakeAll();
     }
 }
@@ -314,6 +333,7 @@ quint32 HonaLowLevelAPI::hsruParserInt123C(const QVector<quint32>& honaData,
     {
         if((honaData[Ind] & 0xFF000000) == 0x0F000000)
         {
+            tempHonaPacketInt123C = HonaPacket();
             tempHonaPacketInt123C.setPacketType(honaPacketType::interrogationMode123C);
             packetLenInt123C = 6;
             tempHonaPacketInt123C.setPacketNumber(honaData[Ind] & 0x0000FFFF);
@@ -321,7 +341,7 @@ quint32 HonaLowLevelAPI::hsruParserInt123C(const QVector<quint32>& honaData,
                 (lastPNInt123C + 1)) & (lastPNInt123C > 0))
             {
                 lossFound +=
-                        ((tempHonaPacketInt123C.getPacketNumber() - lastPNInt123C + 65536) % 65536 - 1);
+                    ((tempHonaPacketInt123C.getPacketNumber() - lastPNInt123C + 65536) % 65536 - 1);
             }
             lastPNInt123C = tempHonaPacketInt123C.getPacketNumber();
             if(nextInt123C > 0)
@@ -336,8 +356,7 @@ quint32 HonaLowLevelAPI::hsruParserInt123C(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x20000000) && (nextInt123C == 2))
         {
             tempHonaPacketInt123C.setToa((tempHonaPacketInt123C.getToa()) +
-                                         (static_cast<quint64>(honaData[Ind] & 0x0000FFFF) <<
-                                          28));
+                (static_cast<quint64>(honaData[Ind] & 0x0000FFFF) <<28));
 
             tempHonaPacketInt123C.setPa2((honaData[Ind] & 0x0FFF0000) >> 16);
             nextInt123C = 3;
@@ -351,23 +370,16 @@ quint32 HonaLowLevelAPI::hsruParserInt123C(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x40000000) && (nextInt123C == 4))
         {
             tempHonaPacketInt123C.setPa1(honaData[Ind] & 0x0000FFFF);
-            tempHonaPacketInt123C.setPa2(tempHonaPacketInt123C.getPa2() +
-                                         ((honaData[Ind] & 0x000F0000) >> 4));
-            tempHonaPacketInt123C.setPa3(tempHonaPacketInt123C.getPa3() +
-                                         ((honaData[Ind] & 0x00F00000) >> 8));
+            tempHonaPacketInt123C.setPa2(tempHonaPacketInt123C.getPa2() + ((honaData[Ind] & 0x000F0000) >> 4));
+            tempHonaPacketInt123C.setPa3(tempHonaPacketInt123C.getPa3() + ((honaData[Ind] & 0x00F00000) >> 8));
             nextInt123C = 5;
         }
         else if(((honaData[Ind] & 0xF0000000) == 0x50000000) && (nextInt123C == 5))
         {
-            tempHonaPacketInt123C.setCodeM(
-                        (static_cast<quint64>(honaData[Ind] & 0x0000001F)) << 59);
+            tempHonaPacketInt123C.setCodeM((static_cast<quint64>(honaData[Ind] & 0x0000001F)) << 59);
             tempHonaPacketInt123C.setCodeL(0);
             nextInt123C = 6;
         }
-        else if(honaData[Ind] == 0xEEEEEEEE)
-        {
-            break;
-        }
 
         if(nextInt123C == packetLenInt123C)
         {
@@ -378,6 +390,9 @@ quint32 HonaLowLevelAPI::hsruParserInt123C(const QVector<quint32>& honaData,
             }
             nextInt123C = 0;
         }
+        else if ( (honaData[Ind] & 0xFFFFFFFF) == 0xEEEEEEEE){
+            break;
+        }
     }
 
     return lossFound;
@@ -392,6 +407,7 @@ quint32 HonaLowLevelAPI::hsruParserRes123C(const QVector<quint32>& honaData,
     {
         if((honaData[Ind] & 0xFF000000) == 0x0F000000)
         {
+            tempHonaPacketRes123C = HonaPacket();
             tempHonaPacketRes123C.setPacketType(honaPacketType::responseMode123C);
             packetLenRes123C = 6;
             tempHonaPacketRes123C.setPacketNumber(honaData[Ind] & 0x0000FFFF);
@@ -399,7 +415,7 @@ quint32 HonaLowLevelAPI::hsruParserRes123C(const QVector<quint32>& honaData,
                 (lastPNRes123C + 1)) & (lastPNRes123C > 0))
             {
                 lossFound +=
-                        ((tempHonaPacketRes123C.getPacketNumber() - lastPNRes123C + 65536) % 65536 - 1);
+                    ((tempHonaPacketRes123C.getPacketNumber() - lastPNRes123C + 65536) % 65536 - 1);
             }
             lastPNRes123C = tempHonaPacketRes123C.getPacketNumber();
             if(nextRes123C > 0)
@@ -414,8 +430,7 @@ quint32 HonaLowLevelAPI::hsruParserRes123C(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x20000000) && (nextRes123C == 2))
         {
             tempHonaPacketRes123C.setToa(tempHonaPacketRes123C.getToa() +
-                                         ((static_cast<quint64>(honaData[Ind] & 0x0000FFFF)) <<
-                                          28));
+                ((static_cast<quint64>(honaData[Ind] & 0x0000FFFF)) << 28));
             tempHonaPacketRes123C.setPa2((honaData[Ind] & 0x0FFF0000) >> 16);
             nextRes123C = 3;
         }
@@ -430,23 +445,19 @@ quint32 HonaLowLevelAPI::hsruParserRes123C(const QVector<quint32>& honaData,
             tempHonaPacketRes123C.setPa1(honaData[Ind] & 0x0000FFFF);
 
             tempHonaPacketRes123C.setPa2(tempHonaPacketRes123C.getPa2() +
-                                         ((honaData[Ind] & 0x000F0000) >> 4));
+                ((honaData[Ind] & 0x000F0000) >> 4));
             tempHonaPacketRes123C.setPa3(tempHonaPacketRes123C.getPa3() +
-                                         ((honaData[Ind] & 0x00F00000) >> 8));
+                ((honaData[Ind] & 0x00F00000) >> 8));
             nextRes123C = 5;
         }
         else if(((honaData[Ind] & 0xF0000000) == 0x50000000) && (nextRes123C == 5))
         {
             tempHonaPacketRes123C.setCodeM(
-                        (static_cast<quint64>(honaData[Ind] & 0x00001FFF)) << 51);
+                (static_cast<quint64>(honaData[Ind] & 0x00001FFF)) << 51);
             tempHonaPacketRes123C.setCodeL(0);
 
             nextRes123C = 6;
         }
-        else if(honaData[Ind] == 0xEEEEEEEE)
-        {
-            break;
-        }
 
         if(nextRes123C == packetLenRes123C)
         {
@@ -457,6 +468,9 @@ quint32 HonaLowLevelAPI::hsruParserRes123C(const QVector<quint32>& honaData,
             }
             nextRes123C = 0;
         }
+        else if ( (honaData[Ind] & 0xFFFFFFFF) == 0xEEEEEEEE){
+            break;
+        }
     }
     return lossFound;
 }
@@ -470,6 +484,7 @@ quint32 HonaLowLevelAPI::hsruParserIntS(const QVector<quint32>& honaData,
     {
         if((honaData[Ind] & 0xFF000000) == 0x0F000000)
         {
+            tempHonaPacketIntS = HonaPacket();
             qint32 TypeVal = (honaData[Ind] & 0x00F00000) >> 20;
             if(TypeVal == 2)
             {
@@ -485,7 +500,7 @@ quint32 HonaLowLevelAPI::hsruParserIntS(const QVector<quint32>& honaData,
             if((tempHonaPacketIntS.getPacketNumber() != (lastPNIntS + 1)) & (lastPNIntS > 0))
             {
                 lossFound +=
-                        ((tempHonaPacketIntS.getPacketNumber() - lastPNIntS + 65536) % 65536 - 1);
+                    ((tempHonaPacketIntS.getPacketNumber() - lastPNIntS + 65536) % 65536 - 1);
             }
             lastPNIntS = tempHonaPacketIntS.getPacketNumber();
             if(nextIntS > 0)
@@ -500,8 +515,7 @@ quint32 HonaLowLevelAPI::hsruParserIntS(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x20000000) && (nextIntS == 2))
         {
             tempHonaPacketIntS.setToa(tempHonaPacketIntS.getToa() +
-                                      ((static_cast<quint64>(honaData[Ind] & 0x0000FFFF)) <<
-                                       28));
+                ((static_cast<quint64>(honaData[Ind] & 0x0000FFFF)) << 28));
             tempHonaPacketIntS.setPa2((honaData[Ind] & 0x0FFF0000) >> 16);
             nextIntS = 3;
         }
@@ -516,7 +530,7 @@ quint32 HonaLowLevelAPI::hsruParserIntS(const QVector<quint32>& honaData,
             tempHonaPacketIntS.setPa1(honaData[Ind] & 0x0000FFFF);
             tempHonaPacketIntS.setPa2(tempHonaPacketIntS.getPa2() + ((honaData[Ind] & 0x000F0000)));
             tempHonaPacketIntS.setPa3(tempHonaPacketIntS.getPa3() +
-                                      ((honaData[Ind] & 0x00F00000) >> 4));
+                ((honaData[Ind] & 0x00F00000) >> 4));
             nextIntS = 5;
         }
         else if(((honaData[Ind] & 0xF0000000) == 0x50000000) && (nextIntS == 5))
@@ -528,7 +542,7 @@ quint32 HonaLowLevelAPI::hsruParserIntS(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x60000000) && (nextIntS == 6))
         {
             tempHonaPacketIntS.setCodeM(tempHonaPacketIntS.getCodeM() +
-                                        ((static_cast<quint64>(honaData[Ind] & 0x0FFFFFFF)) << 36));
+                ((static_cast<quint64>(honaData[Ind] & 0x0FFFFFFF)) << 36));
             tempHonaPacketIntS.setCodeL(0);
             nextIntS = 7;
         }
@@ -541,13 +555,9 @@ quint32 HonaLowLevelAPI::hsruParserIntS(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x80000000) && (nextIntS == 8))
         {
             tempHonaPacketIntS.setCodeM(tempHonaPacketIntS.getCodeM() +
-                                        ((static_cast<quint64>(honaData[Ind] & 0x0FFFFFFF)) << 36));
+                ((static_cast<quint64>(honaData[Ind] & 0x0FFFFFFF)) << 36));
             nextIntS = 9;
         }
-        else if(honaData[Ind] == 0xEEEEEEEE)
-        {
-            break;
-        }
 
         if(nextIntS == packetLenIntS)
         {
@@ -558,6 +568,9 @@ quint32 HonaLowLevelAPI::hsruParserIntS(const QVector<quint32>& honaData,
             }
             nextIntS = 0;
         }
+        else if ( (honaData[Ind] & 0xFFFFFFFF) == 0xEEEEEEEE){
+            break;
+        }
     }
 
     return lossFound;
@@ -572,6 +585,7 @@ quint32 HonaLowLevelAPI::hsruParserResS(const QVector<quint32>& honaData,
     {
         if((honaData[Ind] & 0xFF000000) == 0x0F000000)
         {
+            tempHonaPacketIntS = HonaPacket();
             qint32 TypeVal = (honaData[Ind] & 0x00F00000) >> 20;
             if(TypeVal == 4)
             {
@@ -587,7 +601,7 @@ quint32 HonaLowLevelAPI::hsruParserResS(const QVector<quint32>& honaData,
             if((tempHonaPacketResS.getPacketNumber() != (lastPNResS + 1)) & (lastPNResS > 0))
             {
                 lossFound +=
-                        ((tempHonaPacketResS.getPacketNumber() - lastPNResS + 65536) % 65536 - 1);
+                    ((tempHonaPacketResS.getPacketNumber() - lastPNResS + 65536) % 65536 - 1);
             }
             lastPNResS = tempHonaPacketResS.getPacketNumber();
             if(nextResS > 0)
@@ -602,8 +616,7 @@ quint32 HonaLowLevelAPI::hsruParserResS(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x20000000) && (nextResS == 2))
         {
             tempHonaPacketResS.setToa(tempHonaPacketResS.getToa() +
-                                      ((static_cast<quint64>(honaData[Ind] & 0x0000FFFF)) <<
-                                       28));
+                ((static_cast<quint64>(honaData[Ind] & 0x0000FFFF)) << 28));
             tempHonaPacketResS.setPa2((honaData[Ind] & 0x0FFF0000) >> 16);
             nextResS = 3;
         }
@@ -617,8 +630,7 @@ quint32 HonaLowLevelAPI::hsruParserResS(const QVector<quint32>& honaData,
         {
             tempHonaPacketResS.setPa1(honaData[Ind] & 0x0000FFFF);
             tempHonaPacketResS.setPa2(tempHonaPacketResS.getPa2() + ((honaData[Ind] & 0x000F0000)));
-            tempHonaPacketResS.setPa3(tempHonaPacketResS.getPa3() +
-                                      ((honaData[Ind] & 0x00F00000) >> 4));
+            tempHonaPacketResS.setPa3(tempHonaPacketResS.getPa3() +((honaData[Ind] & 0x00F00000) >> 4));
             nextResS = 5;
         }
         else if(((honaData[Ind] & 0xF0000000) == 0x50000000) && (nextResS == 5))
@@ -630,7 +642,7 @@ quint32 HonaLowLevelAPI::hsruParserResS(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x60000000) && (nextResS == 6))
         {
             tempHonaPacketResS.setCodeM(tempHonaPacketResS.getCodeM() +
-                                        ((static_cast<quint64>(honaData[Ind] & 0x0FFFFFFF)) << 36));
+                ((static_cast<quint64>(honaData[Ind] & 0x0FFFFFFF)) << 36));
             tempHonaPacketResS.setCodeL(0);
             nextResS = 7;
         }
@@ -643,23 +655,21 @@ quint32 HonaLowLevelAPI::hsruParserResS(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x80000000) && (nextResS == 8))
         {
             tempHonaPacketResS.setCodeM(tempHonaPacketResS.getCodeM() +
-                                        ((static_cast<quint64>(honaData[Ind] & 0x0FFFFFFF)) << 36));
+                ((static_cast<quint64>(honaData[Ind] & 0x0FFFFFFF)) << 36));
             nextResS = 9;
         }
-        else if(honaData[Ind] == 0xEEEEEEEE)
-        {
-            break;
-        }
-
         if(nextResS == packetLenResS)
         {
             if(isValid(tempHonaPacketResS))
             {
-                tempHonaPacketResS.setToa((tempHonaPacketResS.getToa() / 8) + toaStartBoard);
+                tempHonaPacketResS.setToa((tempHonaPacketResS.getToa() / 8) + toaStartBoard);;
                 honaPacketList.append(tempHonaPacketResS);
             }
             nextResS = 0;
         }
+        else if ( (honaData[Ind] & 0xFFFFFFFF) == 0xEEEEEEEE){
+            break;
+        }
     }
 
     return lossFound;
@@ -675,13 +685,14 @@ quint32 HonaLowLevelAPI::hsruParserInt4(const QVector<quint32>& honaData,
     {
         if((honaData[Ind] & 0xFF000000) == 0x0F000000)
         {
+            tempHonaPacketInt4 = HonaPacket();
             tempHonaPacketInt4.setPacketType(honaPacketType::interrogationMode4);
             packetLenInt4 = 7;
             tempHonaPacketInt4.setPacketNumber(honaData[Ind] & 0x0000FFFF);
             if((tempHonaPacketInt4.getPacketNumber() != (lastPNInt4 + 1)) & (lastPNInt4 > 0))
             {
                 lossFound +=
-                        ((tempHonaPacketInt4.getPacketNumber() - lastPNInt4 + 65536) % 65536 - 1);
+                    ((tempHonaPacketInt4.getPacketNumber() - lastPNInt4 + 65536) % 65536 - 1);
             }
             lastPNInt4 = tempHonaPacketInt4.getPacketNumber();
             if(nextInt4 > 0)
@@ -696,8 +707,7 @@ quint32 HonaLowLevelAPI::hsruParserInt4(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x20000000) && (nextInt4 == 2))
         {
             tempHonaPacketInt4.setToa(tempHonaPacketInt4.getToa() +
-                                      ((static_cast<quint64>(honaData[Ind] & 0x0000FFFF)) <<
-                                       28));
+                ((static_cast<quint64>(honaData[Ind] & 0x0000FFFF)) << 28));
             tempHonaPacketInt4.setPa2((honaData[Ind] & 0x0FFF0000) >> 16);
             nextInt4 = 3;
         }
@@ -711,9 +721,9 @@ quint32 HonaLowLevelAPI::hsruParserInt4(const QVector<quint32>& honaData,
         {
             tempHonaPacketInt4.setPa1(honaData[Ind] & 0x0000FFFF);
             tempHonaPacketInt4.setPa2(tempHonaPacketInt4.getPa2() +
-                                      ((honaData[Ind] & 0x000F0000) >> 4));
+                ((honaData[Ind] & 0x000F0000) >> 4));
             tempHonaPacketInt4.setPa3(tempHonaPacketInt4.getPa3() +
-                                      ((honaData[Ind] & 0x00F00000) >> 8));
+                ((honaData[Ind] & 0x00F00000) >> 8));
             nextInt4 = 5;
         }
         else if(((honaData[Ind] & 0xF0000000) == 0x50000000) && (nextInt4 == 5))
@@ -726,14 +736,10 @@ quint32 HonaLowLevelAPI::hsruParserInt4(const QVector<quint32>& honaData,
         {
             tempHonaPacketInt4.setPa4(honaData[Ind] & 0x0000FFFF);
             tempHonaPacketInt4.setCodeL(tempHonaPacketInt4.getCodeL() +
-                                        ((static_cast<quint64>(honaData[Ind] & 0x000F0000)) << 12));
+                (static_cast<quint64>(honaData[Ind] & 0x000F0000) << 12));
             tempHonaPacketInt4.setm4Status(static_cast<quint8>((honaData[Ind] & 0x0F000000) >> 20));
             nextInt4 = 7;
         }
-        else if(honaData[Ind] == 0xEEEEEEEE)
-        {
-            break;
-        }
 
         if(nextInt4 == packetLenInt4)
         {
@@ -744,6 +750,9 @@ quint32 HonaLowLevelAPI::hsruParserInt4(const QVector<quint32>& honaData,
             }
             nextInt4 = 0;
         }
+        else if ( (honaData[Ind] & 0xFFFFFFFF) == 0xEEEEEEEE){
+            break;
+        }
     }
 
     return lossFound;
@@ -758,13 +767,14 @@ quint32 HonaLowLevelAPI::hsruParserRes4(const QVector<quint32>& honaData,
     {
         if((honaData[Ind] & 0xFF000000) == 0x0F000000)
         {
+            tempHonaPacketInt4 = HonaPacket();
             tempHonaPacketRes4.setPacketType(honaPacketType::responseMode4);
             packetLenRes4 = 5;
             tempHonaPacketRes4.setPacketNumber(honaData[Ind] & 0x0000FFFF);
             if((tempHonaPacketRes4.getPacketNumber() != (lastPNRes4 + 1)) & (lastPNRes4 > 0))
             {
                 lossFound +=
-                        ((tempHonaPacketRes4.getPacketNumber() - lastPNRes4 + 65536) % 65536 - 1);
+                    ((tempHonaPacketRes4.getPacketNumber() - lastPNRes4 + 65536) % 65536 - 1);
             }
             lastPNRes4 = tempHonaPacketRes4.getPacketNumber();
             if(nextRes4 > 0)
@@ -779,8 +789,7 @@ quint32 HonaLowLevelAPI::hsruParserRes4(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x20000000) && (nextRes4 == 2))
         {
             tempHonaPacketRes4.setToa(tempHonaPacketRes4.getToa() +
-                                      (static_cast<quint64>(honaData[Ind] & 0x0000FFFF) <<
-                                       28));
+                (static_cast<quint64>(honaData[Ind] & 0x0000FFFF) << 28));
             tempHonaPacketRes4.setPa2((honaData[Ind] & 0x0FFF0000) >> 16);
             nextRes4 = 3;
         }
@@ -794,15 +803,11 @@ quint32 HonaLowLevelAPI::hsruParserRes4(const QVector<quint32>& honaData,
         {
             tempHonaPacketRes4.setPa1(honaData[Ind] & 0x0000FFFF);
             tempHonaPacketRes4.setPa2(tempHonaPacketRes4.getPa2() +
-                                      ((honaData[Ind] & 0x000F0000) >> 4));
+                ((honaData[Ind] & 0x000F0000) >> 4));
             tempHonaPacketRes4.setPa3(tempHonaPacketRes4.getPa3() +
-                                      ((honaData[Ind] & 0x00F00000) >> 8));
+                ((honaData[Ind] & 0x00F00000) >> 8));
             nextRes4 = 5;
         }
-        else if(honaData[Ind] == 0xEEEEEEEE)
-        {
-            break;
-        }
 
         if(nextRes4 == packetLenRes4)
         {
@@ -813,6 +818,9 @@ quint32 HonaLowLevelAPI::hsruParserRes4(const QVector<quint32>& honaData,
             }
             nextRes4 = 0;
         }
+        else if ( (honaData[Ind] & 0xFFFFFFFF) == 0xEEEEEEEE){
+            break;
+        }
     }
 
     return lossFound;
@@ -827,6 +835,7 @@ quint32 HonaLowLevelAPI::hsruParserSinglePulse(const QVector<quint32>& honaData,
     {
         if((honaData[Ind] & 0xFF000000) == 0x0F000000)
         {
+            tempHonaPacketSinglePulse = HonaPacket();
             tempHonaPacketSinglePulse.setPacketType(honaPacketType::singlePulseMode4);
             packetLenSinglePulse = 5;
             tempHonaPacketSinglePulse.setPacketNumber(honaData[Ind] & 0x0000FFFF);
@@ -834,9 +843,9 @@ quint32 HonaLowLevelAPI::hsruParserSinglePulse(const QVector<quint32>& honaData,
                 (lastPNSinglePulse + 1)) & (lastPNSinglePulse > 0))
             {
                 lossFound +=
-                        ((tempHonaPacketSinglePulse.getPacketNumber() - lastPNSinglePulse + 65536) %
-                         65536 -
-                         1);
+                    ((tempHonaPacketSinglePulse.getPacketNumber() - lastPNSinglePulse + 65536) %
+                        65536 -
+                        1);
             }
             lastPNSinglePulse = tempHonaPacketSinglePulse.getPacketNumber();
             if(nextSinglePulse > 0)
@@ -846,14 +855,14 @@ quint32 HonaLowLevelAPI::hsruParserSinglePulse(const QVector<quint32>& honaData,
         else if(((honaData[Ind] & 0xF0000000) == 0x10000000) && (nextSinglePulse == 1))
         {
             tempHonaPacketSinglePulse.setToa(static_cast<quint64>(honaData[Ind] &
-                                                                  0x0FFFFFFF));
+                0x0FFFFFFF));
             nextSinglePulse = 2;
         }
         else if(((honaData[Ind] & 0xF0000000) == 0x20000000) && (nextSinglePulse == 2))
         {
             tempHonaPacketSinglePulse.setToa(tempHonaPacketSinglePulse.getToa() +
-                                             ((static_cast<quint64>(honaData[Ind] &
-                                                                    0x0000FFFF)) << 28));
+                ((static_cast<quint64>(honaData[Ind] &
+                    0x0000FFFF)) << 28));
             tempHonaPacketSinglePulse.setPa2((honaData[Ind] & 0x0FFF0000) >> 16);
             nextSinglePulse = 3;
         }
@@ -867,26 +876,25 @@ quint32 HonaLowLevelAPI::hsruParserSinglePulse(const QVector<quint32>& honaData,
         {
             tempHonaPacketSinglePulse.setPa1(honaData[Ind] & 0x0000FFFF);
             tempHonaPacketSinglePulse.setPa2(tempHonaPacketSinglePulse.getPa2() +
-                                             ((honaData[Ind] & 0x000F0000) >> 4));
+                ((honaData[Ind] & 0x000F0000) >> 4));
             tempHonaPacketSinglePulse.setPa3(tempHonaPacketSinglePulse.getPa3() +
-                                             ((honaData[Ind] & 0x00F00000) >> 8));
+                ((honaData[Ind] & 0x00F00000) >> 8));
             nextSinglePulse = 5;
         }
-        else if(honaData[Ind] == 0xEEEEEEEE)
-        {
-            break;
-        }
 
         if(nextSinglePulse == packetLenSinglePulse)
         {
             if(isValid(tempHonaPacketSinglePulse))
             {
                 tempHonaPacketSinglePulse.setToa(
-                            (tempHonaPacketSinglePulse.getToa() / 6) + toaStartBoard);
+                    (tempHonaPacketSinglePulse.getToa() / 6) + toaStartBoard);
                 honaPacketList.append(tempHonaPacketSinglePulse);
             }
             nextSinglePulse = 0;
         }
+        else if ( (honaData[Ind] & 0xFFFFFFFF) == 0xEEEEEEEE){
+            break;
+        }
     }
 
     return lossFound;
@@ -921,10 +929,6 @@ QVector<quint32> HonaLowLevelAPI::hsruReadHonaBuffer(honaReceivers receiver)
         throw HonaException();
     }
 
-    qDebug() << " hsruReadHonaBuffer  receiver "<< receiver;
-    for(auto i = 0 ; i < 10; i++)
-        qDebug() << "[" << i << "] " << "0x" << QString::number(honaData[i], 16);
-    qDebug() << "------------------------------------------------------------";
     return honaData;
 }
 
diff --git a/Plx/src/LowLevel/HonaPacket.cpp b/Plx/src/LowLevel/HonaPacket.cpp
index 7ef7edf..2b0e1ad 100755
--- a/Plx/src/LowLevel/HonaPacket.cpp
+++ b/Plx/src/LowLevel/HonaPacket.cpp
@@ -2,6 +2,19 @@
 
 HonaPacket::HonaPacket()
 {
+    m_PacketType = honaPacketType::singlePulseMode4;
+    m_PacketNumber = 0;
+    m_Toa = 0;
+    m_Doa = 0;
+    m_Pa1 = 0;
+    m_Pa2 = 0;
+    m_Pa3 = 0;
+    m_Pa4 = 0;
+    m_Code = 0;
+    m_CodeL = 0;
+    m_CodeM = 0;
+    m4Status = 0;
+
 }
 
 /*************************************************************************************************/
diff --git a/Plxlibrary/Aardvark.h b/Plxlibrary/Aardvark.h
new file mode 100755
index 0000000..5399879
--- /dev/null
+++ b/Plxlibrary/Aardvark.h
@@ -0,0 +1,952 @@
+/*=========================================================================
+| Aardvark Interface Library
+|--------------------------------------------------------------------------
+| Copyright (c) 2002-2019 Total Phase, Inc.
+| All rights reserved.
+| www.totalphase.com
+|
+| Redistribution and use in source and binary forms, with or without
+| modification, are permitted provided that the following conditions
+| are met:
+|
+| - Redistributions of source code must retain the above copyright
+|   notice, this list of conditions and the following disclaimer.
+|
+| - Redistributions in binary form must reproduce the above copyright
+|   notice, this list of conditions and the following disclaimer in the
+|   documentation and/or other materials provided with the distribution.
+|
+| - Neither the name of Total Phase, Inc. nor the names of its
+|   contributors may be used to endorse or promote products derived from
+|   this software without specific prior written permission.
+|
+| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+| FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+| COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+| INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+| BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+| LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+| CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+| LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+| ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+| POSSIBILITY OF SUCH DAMAGE.
+|--------------------------------------------------------------------------
+| To access Aardvark devices through the API:
+|
+| 1) Use one of the following shared objects:
+|      aardvark.so      --  Linux shared object
+|      aardvark.dll     --  Windows dynamic link library
+|
+| 2) Along with one of the following language modules:
+|      aardvark.c/h     --  C/C++ API header file and interface module
+|      aardvark_py.py   --  Python API
+|      aardvark.bas     --  Visual Basic 6 API
+|      aardvark.cs      --  C# .NET source
+|      aardvark_net.dll --  Compiled .NET binding
+ ========================================================================*/
+
+
+#ifndef __aardvark_h__
+#define __aardvark_h__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*=========================================================================
+| TYPEDEFS
+ ========================================================================*/
+#ifndef TOTALPHASE_DATA_TYPES
+#define TOTALPHASE_DATA_TYPES
+
+#ifndef _MSC_VER
+/* C99-compliant compilers (GCC) */
+#include <stdint.h>
+typedef uint8_t   u08;
+typedef uint16_t  u16;
+typedef uint32_t  u32;
+typedef uint64_t  u64;
+typedef int8_t    s08;
+typedef int16_t   s16;
+typedef int32_t   s32;
+typedef int64_t   s64;
+
+#else
+/* Microsoft compilers (Visual C++) */
+typedef unsigned __int8   u08;
+typedef unsigned __int16  u16;
+typedef unsigned __int32  u32;
+typedef unsigned __int64  u64;
+typedef signed   __int8   s08;
+typedef signed   __int16  s16;
+typedef signed   __int32  s32;
+typedef signed   __int64  s64;
+
+#endif /* __MSC_VER */
+
+typedef float   f32;
+typedef double  f64;
+
+#endif /* TOTALPHASE_DATA_TYPES */
+
+
+/*=========================================================================
+| DEBUG
+ ========================================================================*/
+/* Set the following macro to '1' for debugging */
+#define AA_DEBUG 0
+
+
+/*=========================================================================
+| VERSION
+ ========================================================================*/
+#define AA_HEADER_VERSION  0x0528   /* v5.40 */
+
+
+/*=========================================================================
+| STATUS CODES
+ ========================================================================*/
+/*
+ * All API functions return an integer which is the result of the
+ * transaction, or a status code if negative.  The status codes are
+ * defined as follows:
+ */
+enum AardvarkStatus {
+    /* General codes (0 to -99) */
+    AA_OK                        =    0,
+    AA_UNABLE_TO_LOAD_LIBRARY    =   -1,
+    AA_UNABLE_TO_LOAD_DRIVER     =   -2,
+    AA_UNABLE_TO_LOAD_FUNCTION   =   -3,
+    AA_INCOMPATIBLE_LIBRARY      =   -4,
+    AA_INCOMPATIBLE_DEVICE       =   -5,
+    AA_COMMUNICATION_ERROR       =   -6,
+    AA_UNABLE_TO_OPEN            =   -7,
+    AA_UNABLE_TO_CLOSE           =   -8,
+    AA_INVALID_HANDLE            =   -9,
+    AA_CONFIG_ERROR              =  -10,
+
+    /* I2C codes (-100 to -199) */
+    AA_I2C_NOT_AVAILABLE         = -100,
+    AA_I2C_NOT_ENABLED           = -101,
+    AA_I2C_READ_ERROR            = -102,
+    AA_I2C_WRITE_ERROR           = -103,
+    AA_I2C_SLAVE_BAD_CONFIG      = -104,
+    AA_I2C_SLAVE_READ_ERROR      = -105,
+    AA_I2C_SLAVE_TIMEOUT         = -106,
+    AA_I2C_DROPPED_EXCESS_BYTES  = -107,
+    AA_I2C_BUS_ALREADY_FREE      = -108,
+
+    /* SPI codes (-200 to -299) */
+    AA_SPI_NOT_AVAILABLE         = -200,
+    AA_SPI_NOT_ENABLED           = -201,
+    AA_SPI_WRITE_ERROR           = -202,
+    AA_SPI_SLAVE_READ_ERROR      = -203,
+    AA_SPI_SLAVE_TIMEOUT         = -204,
+    AA_SPI_DROPPED_EXCESS_BYTES  = -205,
+
+    /* GPIO codes (-400 to -499) */
+    AA_GPIO_NOT_AVAILABLE        = -400,
+
+    /* I2C bus monitor codes (-500 to -599) */
+    AA_I2C_MONITOR_NOT_AVAILABLE = -500,
+    AA_I2C_MONITOR_NOT_ENABLED   = -501
+};
+#ifndef __cplusplus
+typedef enum AardvarkStatus AardvarkStatus;
+#endif
+
+
+/*=========================================================================
+| GENERAL TYPE DEFINITIONS
+ ========================================================================*/
+/* Aardvark handle type definition */
+typedef int Aardvark;
+
+/*
+ * Deprecated type definitions.
+ *
+ * These are only for use with legacy code and
+ * should not be used for new development.
+ */
+typedef u08 aa_u08;
+
+typedef u16 aa_u16;
+
+typedef u32 aa_u32;
+
+typedef s08 aa_s08;
+
+typedef s16 aa_s16;
+
+typedef s32 aa_s32;
+
+/*
+ * Aardvark version matrix.
+ *
+ * This matrix describes the various version dependencies
+ * of Aardvark components.  It can be used to determine
+ * which component caused an incompatibility error.
+ *
+ * All version numbers are of the format:
+ *   (major << 8) | minor
+ *
+ * ex. v1.20 would be encoded as:  0x0114
+ */
+struct AardvarkVersion {
+    /* Software, firmware, and hardware versions. */
+    u16 software;
+    u16 firmware;
+    u16 hardware;
+
+    /* Firmware requires that software must be >= this version. */
+    u16 sw_req_by_fw;
+
+    /* Software requires that firmware must be >= this version. */
+    u16 fw_req_by_sw;
+
+    /* Software requires that the API interface must be >= this version. */
+    u16 api_req_by_sw;
+};
+#ifndef __cplusplus
+typedef struct AardvarkVersion AardvarkVersion;
+#endif
+
+
+/*=========================================================================
+| GENERAL API
+ ========================================================================*/
+/*
+ * Get a list of ports to which Aardvark devices are attached.
+ *
+ * nelem   = maximum number of elements to return
+ * devices = array into which the port numbers are returned
+ *
+ * Each element of the array is written with the port number.
+ * Devices that are in-use are ORed with AA_PORT_NOT_FREE (0x8000).
+ *
+ * ex.  devices are attached to ports 0, 1, 2
+ *      ports 0 and 2 are available, and port 1 is in-use.
+ *      array => 0x0000, 0x8001, 0x0002
+ *
+ * If the array is NULL, it is not filled with any values.
+ * If there are more devices than the array size, only the
+ * first nmemb port numbers will be written into the array.
+ *
+ * Returns the number of devices found, regardless of the
+ * array size.
+ */
+#define AA_PORT_NOT_FREE 0x8000
+int aa_find_devices (
+    int   num_devices,
+    u16 * devices
+);
+
+
+/*
+ * Get a list of ports to which Aardvark devices are attached.
+ *
+ * This function is the same as aa_find_devices() except that
+ * it returns the unique IDs of each Aardvark device.  The IDs
+ * are guaranteed to be non-zero if valid.
+ *
+ * The IDs are the unsigned integer representation of the 10-digit
+ * serial numbers.
+ */
+int aa_find_devices_ext (
+    int   num_devices,
+    u16 * devices,
+    int   num_ids,
+    u32 * unique_ids
+);
+
+
+/*
+ * Open the Aardvark port.
+ *
+ * The port number is a zero-indexed integer.
+ *
+ * The port number is the same as that obtained from the
+ * aa_find_devices() function above.
+ *
+ * Returns an Aardvark handle, which is guaranteed to be
+ * greater than zero if it is valid.
+ *
+ * This function is recommended for use in simple applications
+ * where extended information is not required.  For more complex
+ * applications, the use of aa_open_ext() is recommended.
+ */
+Aardvark aa_open (
+    int port_number
+);
+
+
+/*
+ * Open the Aardvark port, returning extended information
+ * in the supplied structure.  Behavior is otherwise identical
+ * to aa_open() above.  If 0 is passed as the pointer to the
+ * structure, this function is exactly equivalent to aa_open().
+ *
+ * The structure is zeroed before the open is attempted.
+ * It is filled with whatever information is available.
+ *
+ * For example, if the firmware version is not filled, then
+ * the device could not be queried for its version number.
+ *
+ * This function is recommended for use in complex applications
+ * where extended information is required.  For more simple
+ * applications, the use of aa_open() is recommended.
+ */
+struct AardvarkExt {
+    /* Version matrix */
+    AardvarkVersion   version;
+
+    /* Features of this device. */
+    int               features;
+};
+#ifndef __cplusplus
+typedef struct AardvarkExt AardvarkExt;
+#endif
+
+Aardvark aa_open_ext (
+    int           port_number,
+    AardvarkExt * aa_ext
+);
+
+
+/* Close the Aardvark port. */
+int aa_close (
+    Aardvark aardvark
+);
+
+
+/*
+ * Return the port for this Aardvark handle.
+ *
+ * The port number is a zero-indexed integer.
+ */
+int aa_port (
+    Aardvark aardvark
+);
+
+
+/*
+ * Return the device features as a bit-mask of values, or
+ * an error code if the handle is not valid.
+ */
+#define AA_FEATURE_SPI 0x00000001
+#define AA_FEATURE_I2C 0x00000002
+#define AA_FEATURE_GPIO 0x00000008
+#define AA_FEATURE_I2C_MONITOR 0x00000010
+int aa_features (
+    Aardvark aardvark
+);
+
+
+/*
+ * Return the unique ID for this Aardvark adapter.
+ * IDs are guaranteed to be non-zero if valid.
+ * The ID is the unsigned integer representation of the
+ * 10-digit serial number.
+ */
+u32 aa_unique_id (
+    Aardvark aardvark
+);
+
+
+/*
+ * Return the status string for the given status code.
+ * If the code is not valid or the library function cannot
+ * be loaded, return a NULL string.
+ */
+const char * aa_status_string (
+    int status
+);
+
+
+/*
+ * Enable logging to a file.  The handle must be standard file
+ * descriptor.  In C, a file descriptor can be obtained by using
+ * the ANSI C function "open" or by using the function "fileno"
+ * on a FILE* stream.  A FILE* stream can be obtained using "fopen"
+ * or can correspond to the common "stdout" or "stderr" --
+ * available when including stdlib.h
+ */
+#define AA_LOG_STDOUT 1
+#define AA_LOG_STDERR 2
+int aa_log (
+    Aardvark aardvark,
+    int      level,
+    int      handle
+);
+
+
+/*
+ * Return the version matrix for the device attached to the
+ * given handle.  If the handle is 0 or invalid, only the
+ * software and required api versions are set.
+ */
+int aa_version (
+    Aardvark          aardvark,
+    AardvarkVersion * version
+);
+
+
+/*
+ * Configure the device by enabling/disabling I2C, SPI, and
+ * GPIO functions.
+ */
+enum AardvarkConfig {
+    AA_CONFIG_GPIO_ONLY = 0x00,
+    AA_CONFIG_SPI_GPIO  = 0x01,
+    AA_CONFIG_GPIO_I2C  = 0x02,
+    AA_CONFIG_SPI_I2C   = 0x03,
+    AA_CONFIG_QUERY     = 0x80
+};
+#ifndef __cplusplus
+typedef enum AardvarkConfig AardvarkConfig;
+#endif
+
+#define AA_CONFIG_SPI_MASK 0x00000001
+#define AA_CONFIG_I2C_MASK 0x00000002
+int aa_configure (
+    Aardvark       aardvark,
+    AardvarkConfig config
+);
+
+
+/*
+ * Configure the target power pins.
+ * This is only supported on hardware versions >= 2.00
+ */
+#define AA_TARGET_POWER_NONE 0x00
+#define AA_TARGET_POWER_BOTH 0x03
+#define AA_TARGET_POWER_QUERY 0x80
+int aa_target_power (
+    Aardvark aardvark,
+    u08      power_mask
+);
+
+
+/*
+ * Sleep for the specified number of milliseconds
+ * Accuracy depends on the operating system scheduler
+ * Returns the number of milliseconds slept
+ */
+u32 aa_sleep_ms (
+    u32 milliseconds
+);
+
+
+
+/*=========================================================================
+| ASYNC MESSAGE POLLING
+ ========================================================================*/
+/*
+ * Polling function to check if there are any asynchronous
+ * messages pending for processing. The function takes a timeout
+ * value in units of milliseconds.  If the timeout is < 0, the
+ * function will block until data is received.  If the timeout is 0,
+ * the function will perform a non-blocking check.
+ */
+#define AA_ASYNC_NO_DATA 0x00000000
+#define AA_ASYNC_I2C_READ 0x00000001
+#define AA_ASYNC_I2C_WRITE 0x00000002
+#define AA_ASYNC_SPI 0x00000004
+#define AA_ASYNC_I2C_MONITOR 0x00000008
+int aa_async_poll (
+    Aardvark aardvark,
+    int      timeout
+);
+
+
+
+/*=========================================================================
+| I2C API
+ ========================================================================*/
+/* Free the I2C bus. */
+int aa_i2c_free_bus (
+    Aardvark aardvark
+);
+
+
+/*
+ * Set the I2C bit rate in kilohertz.  If a zero is passed as the
+ * bitrate, the bitrate is unchanged and the current bitrate is
+ * returned.
+ */
+int aa_i2c_bitrate (
+    Aardvark aardvark,
+    int      bitrate_khz
+);
+
+
+/*
+ * Set the bus lock timeout.  If a zero is passed as the timeout,
+ * the timeout is unchanged and the current timeout is returned.
+ */
+int aa_i2c_bus_timeout (
+    Aardvark aardvark,
+    u16      timeout_ms
+);
+
+
+enum AardvarkI2cFlags {
+    AA_I2C_NO_FLAGS          = 0x00,
+    AA_I2C_10_BIT_ADDR       = 0x01,
+    AA_I2C_COMBINED_FMT      = 0x02,
+    AA_I2C_NO_STOP           = 0x04,
+    AA_I2C_SIZED_READ        = 0x10,
+    AA_I2C_SIZED_READ_EXTRA1 = 0x20
+};
+#ifndef __cplusplus
+typedef enum AardvarkI2cFlags AardvarkI2cFlags;
+#endif
+
+/* Read a stream of bytes from the I2C slave device. */
+int aa_i2c_read (
+    Aardvark         aardvark,
+    u16              slave_addr,
+    AardvarkI2cFlags flags,
+    u16              num_bytes,
+    u08 *            data_in
+);
+
+
+enum AardvarkI2cStatus {
+    AA_I2C_STATUS_OK            = 0,
+    AA_I2C_STATUS_BUS_ERROR     = 1,
+    AA_I2C_STATUS_SLA_ACK       = 2,
+    AA_I2C_STATUS_SLA_NACK      = 3,
+    AA_I2C_STATUS_DATA_NACK     = 4,
+    AA_I2C_STATUS_ARB_LOST      = 5,
+    AA_I2C_STATUS_BUS_LOCKED    = 6,
+    AA_I2C_STATUS_LAST_DATA_ACK = 7
+};
+#ifndef __cplusplus
+typedef enum AardvarkI2cStatus AardvarkI2cStatus;
+#endif
+
+/*
+ * Read a stream of bytes from the I2C slave device.
+ * This API function returns the number of bytes read into
+ * the num_read variable.  The return value of the function
+ * is a status code.
+ */
+int aa_i2c_read_ext (
+    Aardvark         aardvark,
+    u16              slave_addr,
+    AardvarkI2cFlags flags,
+    u16              num_bytes,
+    u08 *            data_in,
+    u16 *            num_read
+);
+
+
+/* Write a stream of bytes to the I2C slave device. */
+int aa_i2c_write (
+    Aardvark         aardvark,
+    u16              slave_addr,
+    AardvarkI2cFlags flags,
+    u16              num_bytes,
+    const u08 *      data_out
+);
+
+
+/*
+ * Write a stream of bytes to the I2C slave device.
+ * This API function returns the number of bytes written into
+ * the num_written variable.  The return value of the function
+ * is a status code.
+ */
+int aa_i2c_write_ext (
+    Aardvark         aardvark,
+    u16              slave_addr,
+    AardvarkI2cFlags flags,
+    u16              num_bytes,
+    const u08 *      data_out,
+    u16 *            num_written
+);
+
+
+/*
+ * Do an atomic write+read to an I2C slave device by first
+ * writing a stream of bytes to the I2C slave device and then
+ * reading a stream of bytes back from the same slave device.
+ * This API function returns the number of bytes written into
+ * the num_written variable and the number of bytes read into
+ * the num_read variable.  The return value of the function is
+ * the status given as (read_status << 8) | (write_status).
+ */
+int aa_i2c_write_read (
+    Aardvark         aardvark,
+    u16              slave_addr,
+    AardvarkI2cFlags flags,
+    u16              out_num_bytes,
+    const u08 *      out_data,
+    u16 *            num_written,
+    u16              in_num_bytes,
+    u08 *            in_data,
+    u16 *            num_read
+);
+
+
+/* Enable/Disable the Aardvark as an I2C slave device */
+int aa_i2c_slave_enable (
+    Aardvark aardvark,
+    u08      addr,
+    u16      maxTxBytes,
+    u16      maxRxBytes
+);
+
+
+int aa_i2c_slave_disable (
+    Aardvark aardvark
+);
+
+
+/*
+ * Set the slave response in the event the Aardvark is put
+ * into slave mode and contacted by a Master.
+ */
+int aa_i2c_slave_set_response (
+    Aardvark    aardvark,
+    u08         num_bytes,
+    const u08 * data_out
+);
+
+
+/*
+ * Return number of bytes written from a previous
+ * Aardvark->I2C_master transmission.  Since the transmission is
+ * happening asynchronously with respect to the PC host
+ * software, there could be responses queued up from many
+ * previous write transactions.
+ */
+int aa_i2c_slave_write_stats (
+    Aardvark aardvark
+);
+
+
+/* Read the bytes from an I2C slave reception */
+int aa_i2c_slave_read (
+    Aardvark aardvark,
+    u08 *    addr,
+    u16      num_bytes,
+    u08 *    data_in
+);
+
+
+/* Extended functions that return status code */
+int aa_i2c_slave_write_stats_ext (
+    Aardvark aardvark,
+    u16 *    num_written
+);
+
+
+int aa_i2c_slave_read_ext (
+    Aardvark aardvark,
+    u08 *    addr,
+    u16      num_bytes,
+    u08 *    data_in,
+    u16 *    num_read
+);
+
+
+/*
+ * Enable the I2C bus monitor
+ * This disables all other functions on the Aardvark adapter
+ */
+int aa_i2c_monitor_enable (
+    Aardvark aardvark
+);
+
+
+/* Disable the I2C bus monitor */
+int aa_i2c_monitor_disable (
+    Aardvark aardvark
+);
+
+
+/* Read the data collected by the bus monitor */
+#define AA_I2C_MONITOR_DATA 0x00ff
+#define AA_I2C_MONITOR_NACK 0x0100
+#define AA_I2C_MONITOR_CMD_START 0xff00
+#define AA_I2C_MONITOR_CMD_STOP 0xff01
+int aa_i2c_monitor_read (
+    Aardvark aardvark,
+    u16      num_bytes,
+    u16 *    data
+);
+
+
+/*
+ * Configure the I2C pullup resistors.
+ * This is only supported on hardware versions >= 2.00
+ */
+#define AA_I2C_PULLUP_NONE 0x00
+#define AA_I2C_PULLUP_BOTH 0x03
+#define AA_I2C_PULLUP_QUERY 0x80
+int aa_i2c_pullup (
+    Aardvark aardvark,
+    u08      pullup_mask
+);
+
+
+
+/*=========================================================================
+| SPI API
+ ========================================================================*/
+/*
+ * Set the SPI bit rate in kilohertz.  If a zero is passed as the
+ * bitrate, the bitrate is unchanged and the current bitrate is
+ * returned.
+ */
+int aa_spi_bitrate (
+    Aardvark aardvark,
+    int      bitrate_khz
+);
+
+
+/*
+ * These configuration parameters specify how to clock the
+ * bits that are sent and received on the Aardvark SPI
+ * interface.
+ *
+ *   The polarity option specifies which transition
+ *   constitutes the leading edge and which transition is the
+ *   falling edge.  For example, AA_SPI_POL_RISING_FALLING
+ *   would configure the SPI to idle the SCK clock line low.
+ *   The clock would then transition low-to-high on the
+ *   leading edge and high-to-low on the trailing edge.
+ *
+ *   The phase option determines whether to sample or setup on
+ *   the leading edge.  For example, AA_SPI_PHASE_SAMPLE_SETUP
+ *   would configure the SPI to sample on the leading edge and
+ *   setup on the trailing edge.
+ *
+ *   The bitorder option is used to indicate whether LSB or
+ *   MSB is shifted first.
+ *
+ * See the diagrams in the Aardvark datasheet for
+ * more details.
+ */
+enum AardvarkSpiPolarity {
+    AA_SPI_POL_RISING_FALLING = 0,
+    AA_SPI_POL_FALLING_RISING = 1
+};
+#ifndef __cplusplus
+typedef enum AardvarkSpiPolarity AardvarkSpiPolarity;
+#endif
+
+enum AardvarkSpiPhase {
+    AA_SPI_PHASE_SAMPLE_SETUP = 0,
+    AA_SPI_PHASE_SETUP_SAMPLE = 1
+};
+#ifndef __cplusplus
+typedef enum AardvarkSpiPhase AardvarkSpiPhase;
+#endif
+
+enum AardvarkSpiBitorder {
+    AA_SPI_BITORDER_MSB = 0,
+    AA_SPI_BITORDER_LSB = 1
+};
+#ifndef __cplusplus
+typedef enum AardvarkSpiBitorder AardvarkSpiBitorder;
+#endif
+
+/* Configure the SPI master or slave interface */
+int aa_spi_configure (
+    Aardvark            aardvark,
+    AardvarkSpiPolarity polarity,
+    AardvarkSpiPhase    phase,
+    AardvarkSpiBitorder bitorder
+);
+
+
+/* Write a stream of bytes to the downstream SPI slave device. */
+int aa_spi_write (
+    Aardvark    aardvark,
+    u16         out_num_bytes,
+    const u08 * data_out,
+    u16         in_num_bytes,
+    u08 *       data_in
+);
+
+
+/* Enable/Disable the Aardvark as an SPI slave device */
+int aa_spi_slave_enable (
+    Aardvark aardvark
+);
+
+
+int aa_spi_slave_disable (
+    Aardvark aardvark
+);
+
+
+/*
+ * Set the slave response in the event the Aardvark is put
+ * into slave mode and contacted by a Master.
+ */
+int aa_spi_slave_set_response (
+    Aardvark    aardvark,
+    u08         num_bytes,
+    const u08 * data_out
+);
+
+
+/* Read the bytes from an SPI slave reception */
+int aa_spi_slave_read (
+    Aardvark aardvark,
+    u16      num_bytes,
+    u08 *    data_in
+);
+
+
+/*
+ * Change the output polarity on the SS line.
+ *
+ * Note: When configured as an SPI slave, the Aardvark will
+ * always be setup with SS as active low.  Hence this function
+ * only affects the SPI master functions on the Aardvark.
+ */
+enum AardvarkSpiSSPolarity {
+    AA_SPI_SS_ACTIVE_LOW  = 0,
+    AA_SPI_SS_ACTIVE_HIGH = 1
+};
+#ifndef __cplusplus
+typedef enum AardvarkSpiSSPolarity AardvarkSpiSSPolarity;
+#endif
+
+int aa_spi_master_ss_polarity (
+    Aardvark              aardvark,
+    AardvarkSpiSSPolarity polarity
+);
+
+
+
+/*=========================================================================
+| GPIO API
+ ========================================================================*/
+/*
+ * The following enumerated type maps the named lines on the
+ * Aardvark I2C/SPI line to bit positions in the GPIO API.
+ * All GPIO API functions will index these lines through an
+ * 8-bit masked value.  Thus, each bit position in the mask
+ * can be referred back its corresponding line through the
+ * enumerated type.
+ */
+enum AardvarkGpioBits {
+    AA_GPIO_SCL  = 0x01,
+    AA_GPIO_SDA  = 0x02,
+    AA_GPIO_MISO = 0x04,
+    AA_GPIO_SCK  = 0x08,
+    AA_GPIO_MOSI = 0x10,
+    AA_GPIO_SS   = 0x20
+};
+#ifndef __cplusplus
+typedef enum AardvarkGpioBits AardvarkGpioBits;
+#endif
+
+/*
+ * Configure the GPIO, specifying the direction of each bit.
+ *
+ * A call to this function will not change the value of the pullup
+ * mask in the Aardvark.  This is illustrated by the following
+ * example:
+ *   (1) Direction mask is first set to 0x00
+ *   (2) Pullup is set to 0x01
+ *   (3) Direction mask is set to 0x01
+ *   (4) Direction mask is later set back to 0x00.
+ *
+ * The pullup will be active after (4).
+ *
+ * On Aardvark power-up, the default value of the direction
+ * mask is 0x00.
+ */
+#define AA_GPIO_DIR_INPUT 0
+#define AA_GPIO_DIR_OUTPUT 1
+int aa_gpio_direction (
+    Aardvark aardvark,
+    u08      direction_mask
+);
+
+
+/*
+ * Enable an internal pullup on any of the GPIO input lines.
+ *
+ * Note: If a line is configured as an output, the pullup bit
+ * for that line will be ignored, though that pullup bit will
+ * be cached in case the line is later configured as an input.
+ *
+ * By default the pullup mask is 0x00.
+ */
+#define AA_GPIO_PULLUP_OFF 0
+#define AA_GPIO_PULLUP_ON 1
+int aa_gpio_pullup (
+    Aardvark aardvark,
+    u08      pullup_mask
+);
+
+
+/*
+ * Read the current digital values on the GPIO input lines.
+ *
+ * The bits will be ordered as described by AA_GPIO_BITS.  If a
+ * line is configured as an output, its corresponding bit
+ * position in the mask will be undefined.
+ */
+int aa_gpio_get (
+    Aardvark aardvark
+);
+
+
+/*
+ * Set the outputs on the GPIO lines.
+ *
+ * Note: If a line is configured as an input, it will not be
+ * affected by this call, but the output value for that line
+ * will be cached in the event that the line is later
+ * configured as an output.
+ */
+int aa_gpio_set (
+    Aardvark aardvark,
+    u08      value
+);
+
+
+/*
+ * Block until there is a change on the GPIO input lines.
+ * Pins configured as outputs will be ignored.
+ *
+ * The function will return either when a change has occurred or
+ * the timeout expires.  The timeout, specified in millisecods, has
+ * a precision of ~16 ms. The maximum allowable timeout is
+ * approximately 4 seconds. If the timeout expires, this function
+ * will return the current state of the GPIO lines.
+ *
+ * This function will return immediately with the current value
+ * of the GPIO lines for the first invocation after any of the
+ * following functions are called: aa_configure,
+ * aa_gpio_direction, or aa_gpio_pullup.
+ *
+ * If the function aa_gpio_get is called before calling
+ * aa_gpio_change, aa_gpio_change will only register any changes
+ * from the value last returned by aa_gpio_get.
+ */
+int aa_gpio_change (
+    Aardvark aardvark,
+    u16      timeout
+);
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __aardvark_h__ */
diff --git a/Plxlibrary/ConsFunc.h b/Plxlibrary/ConsFunc.h
new file mode 100755
index 0000000..5c431d7
--- /dev/null
+++ b/Plxlibrary/ConsFunc.h
@@ -0,0 +1,325 @@
+#ifndef _CONSFUNC_H
+#define _CONSFUNC_H
+
+/*******************************************************************************
+ * Copyright 2013-2016 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      ConsFunc.h
+ *
+ * Description:
+ *
+ *      Header file for the Console functions
+ *
+ * Revision History:
+ *
+ *      04-01-16 : PLX SDK v7.30
+ *
+ ******************************************************************************/
+
+
+#if defined(_WIN32) || defined(_WIN64)
+    #include <stdio.h>
+    #include <conio.h>
+    #include <Windows.h>
+    #define PLX_MSWINDOWS
+#elif defined(PLX_LINUX)
+    #include <stdio.h>
+    #include <stdlib.h>
+    #include <unistd.h>
+    #include <termios.h> 
+    #include <sys/ioctl.h> 
+    #include <sys/time.h> 
+    #include <sys/types.h>
+#elif defined(PLX_DOS)
+    #include <stdio.h>
+    #include <conio.h>
+    #include <string.h>
+    #include <unistd.h>
+    #include <dpmi.h>
+#endif
+
+
+
+
+/*************************************
+ *          Definitions
+ ************************************/
+#if defined(PLX_MSWINDOWS)
+
+    #define Plx_sleep                   Sleep
+    #define Plx_strcmp                  strcmp
+    #define Plx_strcasecmp              stricmp
+    #define Plx_strncasecmp             strnicmp
+    #define Cons_clear                  Plx_clrscr
+    #define Cons_fflush                 fflush
+    #define Cons_flushinp()             FlushConsoleInputBuffer(GetStdHandle(STD_INPUT_HANDLE))
+    #define Cons_fputs                  Plx_fputs
+    #define Cons_kbhit                  _kbhit
+    #define Cons_getch                  _getch
+    #define Cons_puts                   puts
+    #define Cons_putchar                putchar
+    #define Cons_scanf                  scanf
+    #define Cons_printf                 Plx_printf
+
+#elif defined(PLX_LINUX)
+
+    #define Plx_sleep(arg)              usleep((arg) * 1000)
+    #define Plx_strcmp                  strcmp
+    #define Plx_strcasecmp              strcasecmp
+    #define Plx_strncasecmp             strncasecmp
+    #define Cons_clear                  Plx_clrscr
+    #define Cons_fflush                 fflush
+    #define Cons_flushinp               do {while (Plx_kbhit()) Plx_getch();} while (0)
+    #define Cons_fputs                  Plx_fputs
+    #define Cons_kbhit                  Plx_kbhit
+    #define Cons_getch                  Plx_getch
+    #define Cons_puts                   puts
+    #define Cons_putchar                putchar
+    #define Cons_scanf                  scanf
+    #define Cons_printf                 Plx_printf
+
+#elif defined(PLX_DOS)
+
+    #define Plx_sleep(arg)              usleep((arg) * 1000)
+    #define Plx_strcmp                  strcmp
+    #define Plx_strcasecmp              strcasecmp
+    #define Plx_strncasecmp             strncasecmp
+    #define Cons_clear                  clrscr
+    #define Cons_fflush                 fflush
+    #define Cons_flushinp()             do {while (kbhit()) getch();} while (0)
+    #define Cons_fputs                  Plx_fputs
+    #define Cons_kbhit                  kbhit
+    #define Cons_getch                  getch
+    #define Cons_puts                   puts
+    #define Cons_putchar                putchar
+    #define Cons_scanf                  scanf
+    #define Cons_printf                 Plx_printf
+
+#endif
+
+
+#if !defined(min)
+    #define min(a, b)               (((a) < (b)) ? (a) : (b))
+#endif
+
+
+/******************************************************************
+ * A 64-bit HEX value (0xFFFF FFFF FFFF FFFF) requires 20 decimal
+ * digits or 22 octal digits. The following constant defines the
+ * buffer size used to hold an ANSI string converted from a
+ * 64-bit HEX value.
+ *****************************************************************/
+#define MAX_DECIMAL_BUFFER_SIZE         30
+
+#define DEFAULT_SCREEN_SIZE             25  // Default lines to display before halting, if enabled
+#define SCREEN_THROTTLE_OFFSET          2   // Num lines to offset for halting
+
+#define _Pause                                                \
+    do                                                        \
+    {                                                         \
+        Cons_printf("  -- Press any key to continue --");     \
+        Cons_getch();                                         \
+        Cons_printf("\r                                 \r"); \
+    }                                                         \
+    while(0)
+
+
+#define _PauseWithExit                                                           \
+    do                                                                           \
+    {                                                                            \
+        Cons_printf("  -- Press any key to continue or ESC to exit --");         \
+        if (Cons_getch() == 27)                                                  \
+        {                                                                        \
+            Cons_printf("\r                                                \n"); \
+            ConsoleEnd();                                                        \
+            exit(0);                                                             \
+        }                                                                        \
+        Cons_printf("\r                                                \r");     \
+    }                                                                            \
+    while(0)
+
+// Standard key codes
+#define CONS_KEY_NULL                       '\0'
+#define CONS_KEY_ESCAPE                     27
+#define CONS_KEY_NEWLINE                    '\n'
+#define CONS_KEY_CARRIAGE_RET               '\r'
+#define CONS_KEY_TAB                        '\t'
+#define CONS_KEY_BACKSPACE                  '\b'
+
+// 1st extended key code
+#if defined(PLX_LINUX)
+    #define CONS_KEY_EXT_CODE               91
+    #define CONS_KEY_KEYPAD_CODE            79
+#elif defined(PLX_MSWINDOWS)
+    #define CONS_KEY_EXT_CODE               224
+    #define CONS_KEY_KEYPAD_CODE            1      // For code compatability, not actually used
+#elif defined(PLX_DOS)
+    #define CONS_KEY_EXT_CODE               0
+    #define CONS_KEY_KEYPAD_CODE            1      // For code compatability, not actually used
+#endif
+
+// Extended key codes
+#if defined(PLX_LINUX)
+    #define CONS_KEY_EXT_BACKSPACE          127
+    #define CONS_KEY_ARROW_UP               65
+    #define CONS_KEY_ARROW_DOWN             66
+    #define CONS_KEY_ARROW_LEFT             68
+    #define CONS_KEY_ARROW_RIGHT            67
+    #define CONS_KEY_HOME                   49
+    #define CONS_KEY_HOME_XTERM             72     // Code different in GUI terminal
+    #define CONS_KEY_END                    70
+    #define CONS_KEY_END_XTERM              52     // Code different in GUI terminal
+    #define CONS_KEY_INSERT                 50
+    #define CONS_KEY_DELETE                 51
+    #define CONS_KEY_PAGE_UP                53
+    #define CONS_KEY_PAGE_DOWN              54
+#else
+    #define CONS_KEY_EXT_BACKSPACE          127
+    #define CONS_KEY_ARROW_UP               72
+    #define CONS_KEY_ARROW_DOWN             80
+    #define CONS_KEY_ARROW_LEFT             75
+    #define CONS_KEY_ARROW_RIGHT            77
+    #define CONS_KEY_HOME                   71
+    #define CONS_KEY_HOME_XTERM             254    // Added for code compatability
+    #define CONS_KEY_END                    79
+    #define CONS_KEY_END_XTERM              253    // Added for code compatability
+    #define CONS_KEY_INSERT                 82
+    #define CONS_KEY_DELETE                 83
+    #define CONS_KEY_PAGE_UP                73
+    #define CONS_KEY_PAGE_DOWN              81
+#endif
+
+// Preset cursor sizes/types
+#define CONS_CURSOR_DISABLED                0
+#define CONS_CURSOR_UNDERLINE               20
+#define CONS_CURSOR_INSERT                  70
+#define CONS_CURSOR_DEFAULT                 CONS_CURSOR_UNDERLINE
+
+
+
+
+/*************************************
+ *            Functions
+ ************************************/
+void
+ConsoleInitialize(
+    void
+    );
+
+void
+ConsoleEnd(
+    void
+    );
+
+unsigned short
+ConsoleScreenHeightSet(
+    unsigned short NumLines
+    );
+
+unsigned short
+ConsoleScreenHeightGet(
+    void
+    );
+
+void
+ConsoleCursorPropertiesSet(
+    int size
+    );
+
+unsigned char
+ConsoleIoThrottleGet(
+    void
+    );
+
+void
+ConsoleIoThrottleSet(
+    unsigned char bEnable
+    );
+
+void
+ConsoleIoThrottleReset(
+    void
+    );
+
+void
+ConsoleIoThrottleLock(
+    unsigned char bLock
+    );
+
+void
+ConsoleIoIncrementLine(
+    void
+    );
+
+void
+ConsoleIoOutputDisable(
+    unsigned char bEnable
+    );
+
+int
+Plx_fputs(
+    const char *string,
+    FILE       *stream
+    );
+
+int
+Plx_printf(
+    const char *format,
+    ...
+    );
+
+void
+Plx_clrscr(
+    void
+    );
+
+// Linux-specific functions
+#if defined(PLX_LINUX)
+int
+Plx_kbhit(
+    void
+    );
+
+int
+Plx_getch(
+    void
+    );
+#endif
+
+
+
+#endif
diff --git a/Plxlibrary/Eep_8000.h b/Plxlibrary/Eep_8000.h
new file mode 100755
index 0000000..96b0d7d
--- /dev/null
+++ b/Plxlibrary/Eep_8000.h
@@ -0,0 +1,171 @@
+#ifndef __EEP_8000_H
+#define __EEP_8000_H
+
+/*******************************************************************************
+ * Copyright 2013-2015 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      Eep_8000.h
+ *
+ * Description:
+ *
+ *      The include file for 8000-series EEPROM support functions
+ *
+ * Revision History:
+ *
+ *      08-01-11 : PLX SDK v6.50
+ *
+ ******************************************************************************/
+
+
+#include "PlxTypes.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+/**********************************************
+*               Definitions
+**********************************************/
+#define CONST_CRC_XOR_VALUE             0xDB710641          // Constant used in CRC calculations
+
+// PLX 8000-series EEPROM definitions
+#define PLX8000_EE_CMD_READ             3
+#define PLX8000_EE_CMD_READ_STATUS      5
+#define PLX8000_EE_CMD_WRITE_ENABLE     6
+#define PLX8000_EE_CMD_WRITE_DISABLE    4
+#define PLX8000_EE_CMD_WRITE            2
+#define PLX8000_EE_CMD_WRITE_STATUS     1
+
+
+
+
+/**********************************************
+*               Functions
+**********************************************/
+PLX_STATUS
+Plx8000_EepromPresent(
+    PLX_DEVICE_OBJECT *pdx,
+    U8                *pStatus
+    );
+
+PLX_STATUS
+Plx8000_EepromGetAddressWidth(
+    PLX_DEVICE_OBJECT *pdx,
+    U8                *pWidth
+    );
+
+PLX_STATUS
+Plx8000_EepromSetAddressWidth(
+    PLX_DEVICE_OBJECT *pdx,
+    U8                 width
+    );
+
+PLX_STATUS
+Plx8000_EepromCrcGet(
+    PLX_DEVICE_OBJECT *pdx,
+    U32               *pCrc,
+    U8                *pCrcStatus
+    );
+
+PLX_STATUS
+Plx8000_EepromCrcUpdate(
+    PLX_DEVICE_OBJECT *pdx,
+    U32               *pCrc,
+    BOOLEAN            bUpdateEeprom
+    );
+
+PLX_STATUS
+Plx8000_EepromReadByOffset(
+    PLX_DEVICE_OBJECT *pdx,
+    U32                offset,
+    U32               *pValue
+    );
+
+PLX_STATUS
+Plx8000_EepromWriteByOffset(
+    PLX_DEVICE_OBJECT *pdx,
+    U32                offset,
+    U32                value
+    );
+
+PLX_STATUS
+Plx8000_EepromReadByOffset_16(
+    PLX_DEVICE_OBJECT *pdx,
+    U32                offset,
+    U16               *pValue
+    );
+
+PLX_STATUS
+Plx8000_EepromWriteByOffset_16(
+    PLX_DEVICE_OBJECT *pdx,
+    U32                offset,
+    U16                value
+    );
+
+BOOLEAN
+Plx8000_EepromWaitIdle(
+    PLX_DEVICE_OBJECT *pdx
+    );
+
+BOOLEAN
+Plx8000_EepromSendCommand(
+    PLX_DEVICE_OBJECT *pdx,
+    U32                command
+    );
+
+VOID
+Plx8000_EepromComputeNextCrc(
+    U32 *pCrc,
+    U32  NextEepromValue
+    );
+
+U16
+Plx8000_EepromGetCtrlOffset(
+    PLX_DEVICE_OBJECT *pdx
+    );
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/I2cAaUsb.h b/Plxlibrary/I2cAaUsb.h
new file mode 100755
index 0000000..a7fc4ef
--- /dev/null
+++ b/Plxlibrary/I2cAaUsb.h
@@ -0,0 +1,281 @@
+#ifndef __I2C_AA_USB_H
+#define __I2C_AA_USB_H
+
+/*******************************************************************************
+ * Copyright 2013-2018 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *     I2cAaUsb.h
+ *
+ * Description:
+ *
+ *     The PLX API support function prototypes for Aardark I2C interface
+ *
+ * Revision:
+ *
+ *     01-01-18 : PLX SDK v8.00
+ *
+ ******************************************************************************/
+
+
+#include "PlxIoctl.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+/******************************************
+ *             Definitions
+ ******************************************/
+#define I2C_MAX_DEVICES             10          // Max number of I2C USB devices supported
+#define I2C_MAX_NT_PORTS            2           // Max number of NT ports in single switch
+#define I2C_DEFAULT_CLOCK_RATE      100         // I2C default clock rate in Khz
+#define I2C_CMD_REG_READ            0x04        // I2C read command code
+#define I2C_CMD_REG_WRITE           0x03        // I2C write command code
+#define I2C_CMD_ERROR               ((U32)-1)   // Reserved command value to denote error
+#define I2C_CMD_SKIP                ((U32)-2)   // Reserved command value to denote skip operation
+#define I2C_RETRY_MAX_COUNT         3           // On error, max retry count
+#define I2C_RETRY_DELAY_MS          300         // Delay in ms to wait before command retry
+#define I2C_HIGH_ADDR_OFFSET        0x2CC       // Register to contain high address bits
+#define I2C_HIGH_ADDR_INIT          0xFF
+
+// Various addressing modes, which vary between chips
+#define I2C_ADDR_MODE_STD           0           // Standard (ports only)
+#define I2C_ADDR_MODE_NON_STD       1           // Non-standard
+#define I2C_ADDR_MODE_FULL          2           // Full
+#define I2C_ADDR_MODE_NTV           2           // NT-Virtual
+#define I2C_ADDR_MODE_NTL           1           // NT-Link
+#define I2C_ADDR_MODE_NT_P2P        1           // NT parent P2P
+#define I2C_ADDR_MODE_DMA           3           // DMA & DMA RAM
+#define I2C_ADDR_MODE_ALUT          3           // ALUT
+
+#define I2C_PEX_BASE_ADDR_MASK      0xFF800000  // PEX region base address mask
+#define I2C_PEX_MAX_OFFSET_MASK     0x007FFFFF  // Max I2C addressing (23 bits)
+
+
+
+
+/******************************************
+ *      PLX Device Selection Functions
+ *****************************************/
+PLX_STATUS
+PlxI2c_I2cGetPorts(
+    PLX_API_MODE  ApiMode,
+    U32          *pI2cPorts
+    );
+
+PLX_STATUS
+PlxI2c_DeviceOpen(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+PLX_STATUS
+PlxI2c_DeviceClose(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+PLX_STATUS
+PlxI2c_DeviceFindEx(
+    PLX_DEVICE_KEY *pKey,
+    U16             DeviceNumber,
+    PLX_MODE_PROP  *pModeProp
+    );
+
+
+/******************************************
+ *    Query for Information Functions
+ *****************************************/
+PLX_STATUS
+PlxI2c_I2cVersion(
+    U16          I2cPort,
+    PLX_VERSION *pVersion
+    );
+
+
+/******************************************
+ * Device-specific Register Access Functions
+ *****************************************/
+U32
+PlxI2c_PlxRegisterRead(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    PLX_STATUS        *pStatus,
+    BOOLEAN            bAdjustForPort,
+    U16                bRetryOnError
+    );
+
+PLX_STATUS
+PlxI2c_PlxRegisterWrite(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U32                value,
+    BOOLEAN            bAdjustForPort
+    );
+
+
+/******************************************
+ *     Serial EEPROM Access Functions
+ *****************************************/
+PLX_STATUS
+PlxI2c_EepromPresent(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_EEPROM_STATUS *pStatus
+    );
+
+PLX_STATUS
+PlxI2c_EepromProbe(
+    PLX_DEVICE_OBJECT *pDevice,
+    BOOLEAN           *pFlag
+    );
+
+PLX_STATUS
+PlxI2c_EepromGetAddressWidth(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                *pWidth
+    );
+
+PLX_STATUS
+PlxI2c_EepromSetAddressWidth(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 width
+    );
+
+PLX_STATUS
+PlxI2c_EepromCrcUpdate(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32               *pCrc,
+    BOOLEAN            bUpdateEeprom
+    );
+
+PLX_STATUS
+PlxI2c_EepromCrcGet(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32               *pCrc,
+    U8                *pCrcStatus
+    );
+
+PLX_STATUS
+PlxI2c_EepromReadByOffset(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U32               *pValue
+    );
+
+PLX_STATUS
+PlxI2c_EepromWriteByOffset(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U32                value
+    );
+
+PLX_STATUS
+PlxI2c_EepromReadByOffset_16(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U16               *pValue
+    );
+
+PLX_STATUS
+PlxI2c_EepromWriteByOffset_16(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U16                value
+    );
+
+
+/******************************************
+ *          Multi-VS Functions
+ *****************************************/
+PLX_STATUS
+PlxI2c_MH_GetProperties(
+    PLX_DEVICE_OBJECT   *pDevice,
+    PLX_MULTI_HOST_PROP *pMHProp
+    );
+
+PLX_STATUS
+PlxI2c_MH_MigrateDsPorts(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                VS_Source,
+    U16                VS_Dest,
+    U32                DsPortMask,
+    BOOLEAN            bResetSrc
+    );
+
+
+/******************************************
+ *      Private Support Functions
+ *****************************************/
+U32
+PlxI2c_GenerateCommand(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 I2cOperation,
+    U32                Address,
+    BOOLEAN            bAdjustForPort
+    );
+
+BOOLEAN
+PlxI2c_Driver_Connect(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_MODE_PROP     *pModeProp
+    );
+
+S32
+PlxI2c_Dispatch_IoControl(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                IoControlCode,
+    PLX_PARAMS        *pIoBuffer,
+    U32                Size
+    );
+
+PLX_STATUS
+PlxI2c_ProbeSwitch(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_DEVICE_KEY    *pKey,
+    U16                DeviceNumber,
+    U16               *pNumMatched
+    );
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
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diff --git a/Plxlibrary/MdioSpliceUsb.h b/Plxlibrary/MdioSpliceUsb.h
new file mode 100755
index 0000000..ce14e84
--- /dev/null
+++ b/Plxlibrary/MdioSpliceUsb.h
@@ -0,0 +1,315 @@
+#ifndef __MDIO_SPLICE_USB_H
+#define __MDIO_SPLICE_USB_H
+
+/*******************************************************************************
+ * Copyright 2013-2019 Broadcom, Inc
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/*******************************************************************************
+ *
+ * File Name:
+ *
+ *     MdioSpliceUsb.h
+ *
+ * Description:
+ *
+ *     Header file for Splice MDIO USB interface functions
+ *
+ * Revision History:
+ *
+ *     03-01-18: PLX SDK v8.00
+ *
+ ******************************************************************************/
+
+
+#include "PlxIoctl.h"
+#if defined(PLX_LINUX)
+    #include <dlfcn.h>    // For dynamic library functions
+#endif
+
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/******************************************
+ *             Definitions
+ ******************************************/
+// Defaults for loading the MDIO USB library
+#if defined(PLX_MSWINDOWS)
+    #define MDIO_SPLICE_LIB_NAME                "MdioSpliceUsb.dll"
+    #define MDIO_SPLICE_ROOT_PATH_DEFAULT       "C:\\Plx\\PlxSdk\\MdioSpliceUsb"
+#elif defined(PLX_LINUX)
+    #define MDIO_SPLICE_LIB_NAME                ""
+    #define MDIO_SPLICE_ROOT_PATH_DEFAULT       ""
+
+    // Linux dynamic library load functions for portability
+    #define LoadLibrary( name )                 dlopen( (name), RTLD_LAZY )
+    #define FreeLibrary                         dlclose
+    #define GetProcAddress( hdl, fn )           dlsym( (hdl), (fn) )
+    typedef void*                               HINSTANCE;
+    #define TEXT( str )                         (str)
+    #define __cdecl
+#elif defined(PLX_DOS)
+    #define __cdecl
+#endif
+
+#define MDIO_MAX_DEVICES                        10  // Max MDIO USB devices supported
+#define MDIO_DEFAULT_CLOCK_RATE                 100 // MDIO default clock rate in Khz
+
+// Splice API status codes
+#define MDIO_SPLICE_STATUS_OK                   0
+#define MDIO_SPLICE_STATUS_ERROR                1
+typedef int                                     MDIO_SPLICE_STATUS;
+
+// Invalid entry when looking up an address for corresponding MDIO command
+#define MDIO_ADDR_TABLE_IDX_INVALID             (U16)0xFFFF
+
+// Build a 32-bit ID to identify the last accessed region
+#define MDIO_ACCESS_ID( idx, AddrHigh )         (((U32)(idx) << 16) | (U16)(AddrHigh))
+
+// MDIO command build ([28:24]=DEV  [20:16]=PHY/Port  [15:0]=Address/data)
+#define MDIO_CMD_BUILD( phy, dev, data )        ( ((U32)(dev) << 24) | \
+                                                  ((U32)(phy) << 16) | \
+                                                  ((U32)(data) & 0xFFFF) )
+
+// Set data field ([15:0]) in MDIO command
+#define MDIO_CMD_SET_DATA( cmd, data )          ( (cmd) = ((cmd) & 0xFFFF0000) | \
+                                                          ((data) & 0xFFFF) )
+
+// Register read value to return on error
+#define MDIO_REG_READ_U32_FAIL_VAL              ((U32)-1)
+
+
+
+
+/******************************************
+ *      Device Selection Functions
+ *****************************************/
+PLX_STATUS
+MdioSplice_DeviceOpen(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+PLX_STATUS
+MdioSplice_DeviceClose(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+PLX_STATUS
+MdioSplice_DeviceFindEx(
+    PLX_DEVICE_KEY *pKey,
+    U16             DeviceNumber,
+    PLX_MODE_PROP  *pModeProp
+    );
+
+
+/******************************************
+ *    MDIO Private Support Functions
+ *****************************************/
+BOOLEAN
+MdioSplice_Driver_Connect(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_MODE_PROP     *pModeProp
+    );
+
+S32
+MdioSplice_Dispatch_IoControl(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                IoControlCode,
+    PLX_PARAMS        *pIoBuffer,
+    U32                Size
+    );
+
+
+/******************************************
+ * Device-specific Register Access Functions
+ *****************************************/
+U32
+MdioSplice_PlxRegisterRead(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    PLX_STATUS        *pStatus,
+    BOOLEAN            bAdjustForPort,
+    U16                bRetryOnError
+    );
+
+PLX_STATUS
+MdioSplice_PlxRegisterWrite(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U32                value,
+    BOOLEAN            bAdjustForPort
+    );
+
+
+/******************************************
+ * Private functions
+ *****************************************/
+U16
+MdioGetAccessTableIndex(
+    U32 Address
+    );
+
+
+/******************************************
+ * Splice MDIO library functions
+ *****************************************/
+
+/*************************************************************************************************
+ * Function:	UsbConnect()
+ *
+ * Arguments:	port	-	This port handle will be returned and used in calls to
+ *							Read/Write functions listed below such as
+ *								UsbReadMdio(port),
+ *								UsbWriteMdio(port)
+ *				root	-	Root directory for all the dll, firmware, etc.
+ *				dev		-	Target device "D6S" in this case
+ *				index	-	first Splice board = 0, second = 1
+ *
+ * Description:	Opens a communication link between the application and the USB device.
+ *
+ * Return:      0 - on success otherwise failure.
+ *				1 - Failed to find Splice USB Device
+ *				2 - Failed to connect to Splice Board
+ *				3 - Failed to Program USB Firmware
+ *				4 - Failed to Re-Connect to USB after USB Firmware Programming
+ *				5 - Failed to Program FPGA Firmware
+ *				6 - Failed to Program FPGA Firmware
+ *				7 - Failed to verify FPGA version after FPGA Firmware Programming
+ *************************************************************************************************/
+typedef int (__cdecl *Fn_UsbConnect)(void **port, const char *root, const char *dev, unsigned int index);
+
+
+
+
+/*************************************************************************************************
+ * Function:	UsbDisConnect()
+ * Arguments:	port	-	An opaque port handle of type (void *) returned from
+ *							UsbConnect() function call.
+ *
+ * Description:	Closes the specified port and ends the communication to the USB device.
+ *
+ * Return:      0 on success and 1 on failure.
+ *************************************************************************************************/
+typedef int (__cdecl *Fn_UsbDisConnect)(void *port);
+
+
+
+
+/*************************************************************************************************
+ * Function:	UsbReadMdio()
+ *
+ * Arguments:	port	-	An opaque port handle of type (void *) returned from
+ *							UsbConnect() function call.
+ *				addr	-	This is addr array of size count to read from.
+ *				data 	-	This is data array of size count to read into.
+ *				count 	-	This is the length of data and addr array pairs.
+ *				b32		-	set 1 for 32-bit MDIO, 0 for 16-bit MDIO
+ *
+ * Description:	Reads data from MDIO registers on a device from addr -> (addr + count)
+ *
+ * Return:      0 on success and 1 on failure.
+ *************************************************************************************************/
+typedef int (__cdecl *Fn_UsbReadMdio)(const void *port, const void *addr, void *data, unsigned int count, unsigned int b32);
+
+
+
+
+/*************************************************************************************************
+ * Function:	UsbWriteMdio()
+ *
+ * Arguments:	port	-	An opaque port handle of type (void *) returned from
+ *							UsbConnect() function call.
+ *				addr	-	This is addr array of size count to write to.
+ *						-	Address Format is as Follows:
+ *						-	Bits [28:24] = DEVTYPE
+ *						-	Bits [20:16] = PHYADDR
+ *						-	Bits [15:00] = MDIO Address
+ *				data 	-	This is data array of size count to write to.
+ *				count 	-	This is the length of data and addr array pairs.
+ *				b32		-	set 1 for 32-bit MDIO, 0 for 16-bit MDIO
+ *
+ * Description:	Writes data to MDIO registers on a device from addr -> (addr + count)
+ *
+ * Return:      0 on success and 1 on failure.
+ *************************************************************************************************/
+typedef int (__cdecl *Fn_UsbWriteMdio)(const void *port, const void *addr, const void *data, unsigned int count, unsigned int b32);
+
+
+
+/*************************************************************************************************
+ * Function:	UsbReadCfgReg()
+ *
+ * Arguments:	port	-	An opaque port handle of type (void *) returned from
+ *							UsbConnect() function call.
+ *				addr	-	This is addr array of size count to read from.
+ *						-	Address Format is as Follows:
+ *						-	Bits [28:24] = DEVTYPE
+ *						-	Bits [20:16] = PHYADDR
+ *						-	Bits [15:00] = MDIO Address
+ *				data 	-	This is data array of size count to read into.
+ *				count 	-	This is the length of data and addr array pairs.
+ *
+ * Description:	Reads data from config registers on a device from addr -> (addr + count)
+ *
+ * Return:      0 on success and 1 on failure.
+ *************************************************************************************************/
+typedef int (__cdecl *Fn_UsbReadCfgReg)(const void *port, const void *addr, void *data, unsigned int count);
+
+
+
+/*************************************************************************************************
+ * Function:	UsbWriteCfgReg()
+ *
+ * Arguments:	port	-	An opaque port handle of type (void *) returned from
+ *							UsbConnect() function call.
+ *				addr	-	This is addr array of size count to write to.
+ *				data 	-	This is data array of size count to write to.
+ *				count 	-	This is the length of data and addr array pairs.
+ *
+ * Description:	Wites data to config registers on a device from addr -> (addr + count)
+ *
+ * Return:      0 on success and 1 on failure.
+ *************************************************************************************************/
+typedef int (__cdecl *Fn_UsbWriteCfgReg)(const void *port, const void *addr, void *data, unsigned int count);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/PciRegs.h b/Plxlibrary/PciRegs.h
new file mode 100755
index 0000000..6a18b6f
--- /dev/null
+++ b/Plxlibrary/PciRegs.h
@@ -0,0 +1,345 @@
+#ifndef __PCI_REGS_H
+#define __PCI_REGS_H
+
+/*******************************************************************************
+ * Copyright 2013-2020 Broadcom, Inc.
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      PciRegs.h
+ *
+ * Description:
+ *
+ *      This file defines the generic PCI Configuration Registers
+ *
+ * Revision:
+ *
+ *      01-01-20 : PCI/PCIe SDK v8.10
+ *
+ ******************************************************************************/
+
+
+
+// PCI location max counts
+#define PCI_MAX_BUS                             256     // Max PCI Buses
+#define PCI_MAX_DEV                             32      // Max PCI Slots
+#define PCI_MAX_FUNC                            8       // Max PCI Functions
+
+// PCI config space sizes
+#define PCI_CONFIG_SPACE_SIZE                   0x100   // PCI = 256B
+#define PCIE_CONFIG_SPACE_SIZE                  0x1000  // PCIe = 4K
+
+// PCI register read error values return to software
+#define PCI_CFG_RD_ERR_VAL_8                    ((U8)-1)
+#define PCI_CFG_RD_ERR_VAL_16                   ((U16)-1)
+#define PCI_CFG_RD_ERR_VAL_32                   ((U32)-1)
+#define PCI_CFG_RD_ERR_VAL                      PCI_CFG_RD_ERR_VAL_32
+
+// Special values returned for ID read if CRS SW visibility enabled
+#define PCIE_CFG_RD_CRS_VAL_16                  (U16)0x0001
+#define PCIE_CFG_RD_CRS_VAL_32                  (U32)0xFFFF0001
+
+// PCI Header types
+#define PCI_HDR_TYPE_0                          0       // Endpoint
+#define PCI_HDR_TYPE_1                          1       // PCI-to-PCI bridge
+#define PCI_HDR_TYPE_2                          2       // Cardbus
+#define PCI_NUM_BARS_TYPE_00                    6       // Type 0 total PCI BARs
+#define PCI_NUM_BARS_TYPE_01                    2       // Type 1 total PCI BARs
+
+// Standard PCI registers
+#define PCI_REG_DEV_VEN_ID                      0x00
+#define PCI_REG_CMD_STAT                        0x04
+#define PCI_REG_CLASS_REV                       0x08
+#define PCI_REG_HDR_CACHE_LN                    0x0C
+#define PCI_REG_BAR_0                           0x10
+#define PCI_REG_BAR_1                           0x14
+#define PCI_REG_CAP_PTR                         0x34
+#define PCI_REG_INT_PIN_LN                      0x3C
+
+// Type 0 specific standard registers
+#define PCI_REG_T0_BAR_2                        0x18
+#define PCI_REG_T0_BAR_3                        0x1C
+#define PCI_REG_T0_BAR_4                        0x20
+#define PCI_REG_T0_BAR_5                        0x24
+#define PCI_REG_TO_CARDBUS_PTR                  0x28
+#define PCI_REG_TO_SUBSYS_ID                    0x2C
+#define PCI_REG_TO_EXP_ROM                      0x30
+#define PCI_REG_TO_RSVD_38H                     0x38
+
+// Type 1 specific standard registers
+#define PCI_REG_T1_PRIM_SEC_BUS                 0x18
+#define PCI_REG_T1_IO_BASE_LIM                  0x1C
+#define PCI_REG_T1_MEM_BASE_LIM                 0x20
+#define PCI_REG_T1_PF_MEM_BASE_LIM              0x24
+#define PCI_REG_T1_PF_MEM_BASE_HIGH             0x28
+#define PCI_REG_T1_PF_MEM_LIM_HIGH              0x2C
+#define PCI_REG_T1_IO_BASE_LIM_HIGH             0x30
+#define PCI_REG_T1_EXP_ROM                      0x38
+
+// PCIe 1st capability pointer
+#define PCIE_REG_CAP_PTR                        0x100
+
+
+// PCI Extended Capability IDs
+#define PCI_CAP_ID_NULL                         0x00
+#define PCI_CAP_ID_POWER_MAN                    0x01
+#define PCI_CAP_ID_AGP                          0x02
+#define PCI_CAP_ID_VPD                          0x03
+#define PCI_CAP_ID_SLOT_ID                      0x04
+#define PCI_CAP_ID_MSI                          0x05
+#define PCI_CAP_ID_HOT_SWAP                     0x06
+#define PCI_CAP_ID_PCIX                         0x07
+#define PCI_CAP_ID_HYPER_TRANSPORT              0x08
+#define PCI_CAP_ID_VENDOR_SPECIFIC              0x09
+#define PCI_CAP_ID_DEBUG_PORT                   0x0A
+#define PCI_CAP_ID_RESOURCE_CTRL                0x0B
+#define PCI_CAP_ID_HOT_PLUG                     0x0C
+#define PCI_CAP_ID_BRIDGE_SUB_ID                0x0D
+#define PCI_CAP_ID_AGP_8X                       0x0E
+#define PCI_CAP_ID_SECURE_DEVICE                0x0F
+#define PCI_CAP_ID_PCI_EXPRESS                  0x10
+#define PCI_CAP_ID_MSI_X                        0x11
+#define PCI_CAP_ID_SATA                         0x12
+#define PCI_CAP_ID_ADV_FEATURES                 0x13
+#define PCI_CAP_ID_ENHANCED_ALLOCATION          0x14
+#define PCI_CAP_ID_FLATTENING_PORTAL_BRIDGE     0x15
+
+
+// PCI Express Extended Capability IDs
+#define PCIE_CAP_ID_NULL                        0x000       // Empty capability
+#define PCIE_CAP_ID_ADV_ERROR_REPORTING         0x001       // Advanced Error Reporting (AER)
+#define PCIE_CAP_ID_VIRTUAL_CHANNEL             0x002       // Virtual Channel (VC)
+#define PCIE_CAP_ID_DEV_SERIAL_NUMBER           0x003       // Device Serial Number
+#define PCIE_CAP_ID_POWER_BUDGETING             0x004       // Power Budgeting
+#define PCIE_CAP_ID_RC_LINK_DECLARATION         0x005       // Root Complex Link Declaration
+#define PCIE_CAP_ID_RC_INT_LINK_CONTROL         0x006       // Root Complex Internal Link Control
+#define PCIE_CAP_ID_RC_EVENT_COLLECTOR          0x007       // Root Complex Event Collector Endpoint Association
+#define PCIE_CAP_ID_MF_VIRTUAL_CHANNEL          0x008       // Multi-Function Virtual Channel (MFVC)
+#define PCIE_CAP_ID_VC_WITH_MULTI_FN            0x009       // Virtual Channel with Multi-Function
+#define PCIE_CAP_ID_RC_REG_BLOCK                0x00A       // Root Complex Register Block (RCRB)
+#define PCIE_CAP_ID_VENDOR_SPECIFIC             0x00B       // Vendor-specific (VSEC)
+#define PCIE_CAP_ID_CONFIG_ACCESS_CORR          0x00C       // Configuration Access Correlation
+#define PCIE_CAP_ID_ACCESS_CTRL_SERVICES        0x00D       // Access Control Services (ACS)
+#define PCIE_CAP_ID_ALT_ROUTE_ID_INTERPRET      0x00E       // Alternate Routing-ID Interpretation (ARI)
+#define PCIE_CAP_ID_ADDR_TRANS_SERVICES         0x00F       // Address Translation Services (ATS)
+#define PCIE_CAP_ID_SR_IOV                      0x010       // SR-IOV
+#define PCIE_CAP_ID_MR_IOV                      0x011       // MR-IOV
+#define PCIE_CAP_ID_MULTICAST                   0x012       // Multicast
+#define PCIE_CAP_ID_PAGE_REQUEST                0x013       // Page Request Interface (PRI)
+#define PCIE_CAP_ID_AMD_RESERVED                0x014       // Reserved for AMD
+#define PCIE_CAP_ID_RESIZABLE_BAR               0x015       // Resizable BAR
+#define PCIE_CAP_ID_DYNAMIC_POWER_ALLOC         0x016       // Dynamic Power Allocation (DPA)
+#define PCIE_CAP_ID_TLP_PROCESSING_HINT         0x017       // TLP Processing Hints (TPH)
+#define PCIE_CAP_ID_LATENCY_TOLERANCE_REPORT    0x018       // Latency Tolerance Reporting (LTR)
+#define PCIE_CAP_ID_SECONDARY_PCI_EXPRESS       0x019       // Secondary PCI Express
+#define PCIE_CAP_ID_PROTOCOL_MULTIPLEX          0x01A       // Protocol Multiplexing (PMUX)
+#define PCIE_CAP_ID_PROCESS_ADDR_SPACE_ID       0x01B       // Process Address Space ID (PASID)
+#define PCIE_CAP_ID_LTWT_NOTIF_REQUESTER        0x01C       // Lightweight Notification Requester (LNR)
+#define PCIE_CAP_ID_DS_PORT_CONTAINMENT         0x01D       // Downstream Port Containment (DPC)
+#define PCIE_CAP_ID_L1_PM_SUBSTRATES            0x01E       // L1 Power Management Substrates (L1PM)
+#define PCIE_CAP_ID_PRECISION_TIME_MEAS         0x01F       // Precision Time Measurement (PTM)
+#define PCIE_CAP_ID_PCIE_OVER_M_PHY             0x020       // PCIe over M-PHY (M-PCIe)
+#define PCIE_CAP_ID_FRS_QUEUEING                0x021       // FRS Queueing
+#define PCIE_CAP_ID_READINESS_TIME_REPORTING    0x022       // Readiness Time Reporting
+#define PCIE_CAP_ID_DESIGNATED_VEND_SPECIFIC    0x023       // Designated vendor-specific
+#define PCIE_CAP_ID_VF_RESIZABLE_BAR            0x024       // VF resizable BAR
+#define PCIE_CAP_ID_DATA_LINK_FEATURE           0x025       // Data Link Feature
+#define PCIE_CAP_ID_PHYS_LAYER_16GT             0x026       // Physical Layer 16 GT/s
+#define PCIE_CAP_ID_PHYS_LAYER_16GT_MARGINING   0x027       // Physical Layer 16 GT/s Margining
+#define PCIE_CAP_ID_HIERARCHY_ID                0x028       // Hierarchy ID
+#define PCIE_CAP_ID_NATIVE_PCIE_ENCL_MGMT       0x029       // Native PCIe Enclosure Management (NPEM)
+#define PCIE_CAP_ID_PHYS_LAYER_32GT             0x02A       // Physical Layer 32 GT/s
+#define PCIE_CAP_ID_ALTERNATE_PROTOCOL          0x02B       // Alternate Protocol
+#define PCIE_CAP_ID_SYS_FW_INTERMEDIARY         0x02C       // System Firmware Intermediary (SFI)
+
+
+// Convert encoding of MPS/MRR to bytes (128 * (2 ^ encoded_val))
+#define PCIE_MPS_MRR_TO_BYTES(val)              ( 128 * (1 << (val)) )
+
+
+// PCI device Power Management states (PM Cntrl/Stat [1:0])
+#define PCI_CAP_PM_STATE_D0                     0x00
+#define PCI_CAP_PM_STATE_D1                     0x01
+#define PCI_CAP_PM_STATE_D2                     0x02
+#define PCI_CAP_PM_STATE_D3_HOT                 0x03
+
+
+// Function codes for PCI BIOS operations
+#define PCI_FUNC_ID                             0xb1
+#define PCI_FUNC_BIOS_PRESENT                   0x01
+#define PCI_FUNC_FIND_PCI_DEVICE                0x02
+#define PCI_FUNC_FIND_PCI_CLASS_CODE            0x03
+#define PCI_FUNC_GENERATE_SPECIAL_CYC           0x06
+#define PCI_FUNC_READ_CONFIG_BYTE               0x08
+#define PCI_FUNC_READ_CONFIG_WORD               0x09
+#define PCI_FUNC_READ_CONFIG_DWORD              0x0a
+#define PCI_FUNC_WRITE_CONFIG_BYTE              0x0b
+#define PCI_FUNC_WRITE_CONFIG_WORD              0x0c
+#define PCI_FUNC_WRITE_CONFIG_DWORD             0x0d
+#define PCI_FUNC_GET_IRQ_ROUTING_OPTS           0x0e
+#define PCI_FUNC_SET_PCI_HW_INT                 0x0f
+
+
+// PCI SIG Vendor IDs
+#define PLX_PCI_VENDOR_ID_LSI                   0x1000
+#define PLX_PCI_VENDOR_ID_PLX                   0x10B5
+#define PLX_PCI_VENDOR_ID_BROADCOM              0x14E4
+#define PLX_PCI_VENDOR_ID_AMD                   0x1022
+#define PLX_PCI_VENDOR_ID_HEWLETT_PACKARD       0x103C
+#define PLX_PCI_VENDOR_ID_HP_ENTERPRISE         0x1590
+#define PLX_PCI_VENDOR_ID_HITACHI               0x1054
+#define PLX_PCI_VENDOR_ID_HUAWEI                0x19E5
+#define PLX_PCI_VENDOR_ID_IBM                   0x1014
+#define PLX_PCI_VENDOR_ID_INTEL                 0x8086
+#define PLX_PCI_VENDOR_ID_LENOVO                0x1D49
+#define PLX_PCI_VENDOR_ID_MARVELL               0x1148
+#define PLX_PCI_VENDOR_ID_MATROX                0x102B
+#define PLX_PCI_VENDOR_ID_MELLANOX              0x15B3
+#define PLX_PCI_VENDOR_ID_NETAPP                0x1275
+#define PLX_PCI_VENDOR_ID_NVIDIA                0x10DE
+#define PLX_PCI_VENDOR_ID_QUALCOMM              0x5143
+#define PLX_PCI_VENDOR_ID_REALTEK               0x10EC
+#define PLX_PCI_VENDOR_ID_SAMSUNG               0x144D
+#define PLX_PCI_VENDOR_ID_SEAGATE               0x1BB1
+#define PLX_PCI_VENDOR_ID_TOSHIBA               0x1179
+#define PLX_PCI_VENDOR_ID_WESTERN_DIGITAL       0x1B96
+
+
+// PCIe ReqID support macros
+#define PCIE_REQID_BUILD(bus,dev,fn)            (((U16)(bus) << 8) | ((dev) << 3) | ((fn) << 0))
+#define PCIE_REQID_BUS(ReqId)                   ((U8)((ReqId) >> 8) & 0xFF)
+#define PCIE_REQID_DEV(ReqId)                   ((U8)((ReqId) >> 3) & 0x1F)
+#define PCIE_REQID_FN(ReqId)                    ((U8)((ReqId) >> 0) & 0x7)
+
+
+
+// PCIe TLP format
+typedef enum _PCIE_TLP_FORMAT
+{
+    PCIE_TLP_FORMAT_3DW_NO_DATA             = 0x0,
+    PCIE_TLP_FORMAT_4DW_NO_DATA             = 0x1,
+    PCIE_TLP_FORMAT_3DW_DATA                = 0x2,
+    PCIE_TLP_FORMAT_4DW_DATA                = 0x3,
+    PCIE_TLP_FORMAT_TLP_PREFIX              = 0x4
+} PCIE_TLP_FORMAT;
+
+
+// PCIe TLP Types
+typedef enum _PCIE_TLP_TYPE
+{
+    TLP_TYPE_MEM_READ_32                    = 0x00,
+    TLP_TYPE_MEM_READ_64                    = 0x20,
+    TLP_TYPE_MEM_READ_LOCK_32               = 0x01,
+    TLP_TYPE_MEM_READ_LOCK_64               = 0x21,
+    TLP_TYPE_MEM_WRITE_32                   = 0x40,
+    TLP_TYPE_MEM_WRITE_64                   = 0x60,
+    TLP_TYPE_IO_READ                        = 0x02,
+    TLP_TYPE_IO_WRITE                       = 0x42,
+    TLP_TYPE_CFG_READ_TYPE_0                = 0x04,
+    TLP_TYPE_CFG_WRITE_TYPE_0               = 0x44,
+    TLP_TYPE_CFG_READ_TYPE_1                = 0x05,
+    TLP_TYPE_CFG_WRITE_TYPE_1               = 0x45,
+    TLP_TYPE_MSG_TO_RC                      = 0x30,
+    TLP_TYPE_MSG_BY_ADDRESS                 = 0x31,
+    TLP_TYPE_MSG_BY_ID                      = 0x32,
+    TLP_TYPE_MSG_RC_BROADCAST               = 0x33,
+    TLP_TYPE_MSG_TO_RECEIVER                = 0x34,
+    TLP_TYPE_MSG_GATHERED_TO_RC             = 0x35,
+    TLP_TYPE_MSGD_TO_RC                     = 0x70,
+    TLP_TYPE_MSGD_BY_ADDRESS                = 0x71,
+    TLP_TYPE_MSGD_BY_ID                     = 0x72,
+    TLP_TYPE_MSGD_RC_BROADCAST              = 0x73,
+    TLP_TYPE_MSGD_TO_RECEIVER               = 0x74,
+    TLP_TYPE_MSGD_GATHERED_TO_RC            = 0x75,
+    TLP_TYPE_CPL_NO_DATA                    = 0x0A,
+    TLP_TYPE_CPL_WITH_DATA                  = 0x4A,
+    TLP_TYPE_CPL_LOCKED_NO_DATA             = 0x0B,
+    TLP_TYPE_CPL_LOCKED_WITH_DATA           = 0x4B,
+    TLP_TYPE_FINAL_ENTRY                    = 0xFF      // Must be last entry
+} PCIE_TLP_TYPE;
+
+
+// PCIe Completion TLP status
+typedef enum _PCIE_TLP_CPL_STATUS
+{
+    TLP_CPL_STATUS_SUCCESS                  = 0x00,
+    TLP_CPL_STATUS_UNSUPP_REQ               = 0x01,
+    TLP_CPL_STATUS_CONFIG_RETRY             = 0x02,
+    TLP_CPL_STATUS_COMPLETER_ABORT          = 0x04
+} PCIE_TLP_CPL_STATUS;
+
+
+// PCIe Message TLP routing
+typedef enum _PCIE_TLP_MSG_ROUTE
+{
+    TLP_MSG_ROUTE_TO_RC                     = 0x00,
+    TLP_MSG_ROUTE_BY_ADDR                   = 0x01,
+    TLP_MSG_ROUTE_BY_ID                     = 0x02,
+    TLP_MSG_ROUTE_RC_BROADCAST              = 0x03,
+    TLP_MSG_ROUTE_LOCAL_TERMINATE           = 0x04,
+    TLP_MSG_ROUTE_GATHERED_TO_RC            = 0x05,
+} PCIE_TLP_MSG_ROUTE;
+
+
+// PCIe Message TLP types
+typedef enum _PCIE_TLP_MSG
+{
+    TLP_MSG_UNLOCK                          = 0x00,
+    TLP_MSG_LATENCY_TOLERANCE_REP           = 0x10,
+    TLP_MSG_OPT_BUFF_FLUSH_FILL             = 0x12,
+    TLP_MSG_PM_ACTIVE_STATE_NAK             = 0x14,
+    TLP_MSG_PM_PME                          = 0x18,
+    TLP_MSG_PM_PME_TURN_OFF                 = 0x19,
+    TLP_MSG_PM_PME_TO_ACK                   = 0x1B,
+    TLP_MSG_ERROR_CORRECTABLE               = 0x30,
+    TLP_MSG_ERROR_NON_FATAL                 = 0x31,
+    TLP_MSG_ERROR_FATAL                     = 0x33,
+    TLP_MSG_ASSERT_INTA                     = 0x20,
+    TLP_MSG_ASSERT_INTB                     = 0x21,
+    TLP_MSG_ASSERT_INTC                     = 0x22,
+    TLP_MSG_ASSERT_INTD                     = 0x23,
+    TLP_MSG_DEASSERT_INTA                   = 0x24,
+    TLP_MSG_DEASSERT_INTB                   = 0x25,
+    TLP_MSG_DEASSERT_INTC                   = 0x26,
+    TLP_MSG_DEASSERT_INTD                   = 0x27,
+    TLP_MSG_SET_SLOT_POWER_LIMIT            = 0x50,
+    TLP_MSG_VENDOR_DEFINED_TYPE_0           = 0x7E,
+    TLP_MSG_VENDOR_DEFINED_TYPE_1           = 0x7F,
+    TLP_MSG_FINAL_ENTRY                     = 0xFF      // Must be last entry
+} PCIE_TLP_MSG;
+
+
+
+#endif
diff --git a/Plxlibrary/PciTypes.h b/Plxlibrary/PciTypes.h
new file mode 100755
index 0000000..b715be7
--- /dev/null
+++ b/Plxlibrary/PciTypes.h
@@ -0,0 +1,388 @@
+#ifndef __PCI_TYPES_H
+#define __PCI_TYPES_H
+
+/*******************************************************************************
+ * Copyright 2013-2017 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      PciTypes.h
+ *
+ * Description:
+ *
+ *      This file defines the basic types
+ *
+ * Revision:
+ *
+ *      06-01-19 : PLX SDK v8.00
+ *
+ ******************************************************************************/
+
+
+#if defined(PLX_WDM_DRIVER)
+    #include <wdm.h>            // WDM Driver types
+#endif
+
+#if defined(PLX_NT_DRIVER)
+    #include <ntddk.h>          // NT Kernel Mode Driver (ie PLX Service)
+#endif
+
+#if defined(PLX_MSWINDOWS)
+    #if !defined(PLX_DRIVER)
+        #include <wtypes.h>     // Windows application level types
+    #endif
+#endif
+
+// Must be placed before <linux/types.h> to prevent compile errors
+#if defined(PLX_LINUX) && !defined(PLX_LINUX_DRIVER)
+    #include <memory.h>         // To automatically add mem*() set of functions
+#endif
+
+#if defined(PLX_LINUX) || defined(PLX_LINUX_DRIVER)
+    #include <linux/types.h>    // Linux types
+#endif
+
+#if defined(PLX_LINUX)
+    #include <limits.h>         // For MAX_SCHEDULE_TIMEOUT in Linux applications
+#endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/*******************************************
+ *   Linux Application Level Definitions
+ ******************************************/
+#if defined(PLX_LINUX)
+    typedef __s8                  S8;
+    typedef __u8                  U8;
+    typedef __s16                 S16;
+    typedef __u16                 U16;
+    typedef __s32                 S32;
+    typedef __u32                 U32;
+    typedef __s64                 S64;
+    typedef __u64                 U64;
+    typedef signed long           PLX_INT_PTR;        // For 32/64-bit code compatability
+    typedef unsigned long         PLX_UINT_PTR;
+    typedef int                   HANDLE;
+    typedef int                   PLX_DRIVER_HANDLE;  // Linux-specific driver handle
+
+    #define INVALID_HANDLE_VALUE  (HANDLE)-1
+
+    #if !defined(MAX_SCHEDULE_TIMEOUT)
+        #define MAX_SCHEDULE_TIMEOUT    LONG_MAX
+    #endif
+#endif
+
+
+
+/*******************************************
+ *    Linux Kernel Level Definitions
+ ******************************************/
+#if defined(PLX_LINUX_DRIVER)
+    typedef s8                    S8;
+    typedef u8                    U8;
+    typedef s16                   S16;
+    typedef u16                   U16;
+    typedef s32                   S32;
+    typedef u32                   U32;
+    typedef s64                   S64;
+    typedef u64                   U64;
+    typedef signed long           PLX_INT_PTR;        // For 32/64-bit code compatability
+    typedef unsigned long         PLX_UINT_PTR;
+    typedef int                   PLX_DRIVER_HANDLE;  // Linux-specific driver handle
+#endif
+
+
+
+/*******************************************
+ *      Windows Type Definitions
+ ******************************************/
+#if defined(PLX_MSWINDOWS)
+    typedef signed char           S8;
+    typedef unsigned char         U8;
+    typedef signed short          S16;
+    typedef unsigned short        U16;
+    typedef signed long           S32;
+    typedef unsigned long         U32;
+    typedef signed __int64        S64;
+    typedef unsigned __int64      U64;
+    typedef INT_PTR               PLX_INT_PTR;        // For 32/64-bit code compatability
+    typedef UINT_PTR              PLX_UINT_PTR;
+    typedef HANDLE                PLX_DRIVER_HANDLE;  // Windows-specific driver handle
+
+    #if defined(_DEBUG)
+        #define PLX_DEBUG
+    #endif
+#endif
+
+
+
+/*******************************************
+ *    Windows WDM Driver Compatability
+ ******************************************/
+#if defined(PLX_WDM_DRIVER)
+    // RtlIsNtDdiVersionAvailable supported in Windows Vista & higher
+    #if (WINVER < 0x600)
+        #define RtlIsNtDdiVersionAvailable(ver)     IoIsWdmVersionAvailable( (U8)(ver >> 24), (U8)(ver >> 16) )
+
+        // Windows versions taken from SdkDdkVer.h
+        #define NTDDI_WIN2K                         0x01100000  // WDM=1.10 Winver=5.00
+        #define NTDDI_WINXP                         0x01200000  // WDM=1.20 Winver=5.01
+        #define NTDDI_WS03                          0x01300000  // WDM=1.30 Winver=5.02
+    #endif
+
+    #if (WINVER < 0x601)
+        #define NTDDI_WIN6                          0x06000000
+        #define NTDDI_WIN6SP1                       0x06000100
+        #define NTDDI_VISTA                         NTDDI_WIN6
+        #define NTDDI_WS08                          NTDDI_WIN6SP1
+        #define NTDDI_WIN7                          0x06010000
+    #endif
+
+    #if (WINVER < 0x602)
+        #define NTDDI_WIN8                          0x06020000
+        #define NTDDI_WIN10                         0x0A000000
+    #endif
+
+    #if (WINVER < 0x603)
+        #define NTDDI_WINBLUE                       0x06030000  // Windows 8.1
+    #endif
+
+    #if (WINVER < 0xA00)
+        #define NTDDI_WIN10                         0x0A000000
+    #endif
+
+    // Additional Win8+ DDK definitions
+    #if (NTDDI_VER < NTDDI_WIN8)
+        // More POOL_TYPEs added, needed for no-execute
+        typedef enum _PLX_POOL_TYPE
+        {
+            NonPagedPoolBase                      = 0,
+            NonPagedPoolBaseMustSucceed           = NonPagedPoolBase + 2,
+            NonPagedPoolBaseCacheAligned          = NonPagedPoolBase + 4,
+            NonPagedPoolBaseCacheAlignedMustS     = NonPagedPoolBase + 6,
+
+            NonPagedPoolNx                        = 512,
+            NonPagedPoolNxCacheAligned            = NonPagedPoolNx + 4,
+            NonPagedPoolSessionNx                 = NonPagedPoolNx + 32
+        } PLX_POOL_TYPE;
+
+        // Additional -OR- flags for MM_PAGE_PRIORITY
+        #define MdlMappingNoWrite       0x80000000  // Create the mapping as nowrite
+        #define MdlMappingNoExecute     0x40000000  // Create the mapping as noexecute
+    #endif
+
+    #if (NTDDI_VER < NTDDI_WIN7)
+        // Win7 DDK added typedef's for registered functions for declaration
+        typedef
+        NTSTATUS
+        DRIVER_INITIALIZE(
+            struct _DRIVER_OBJECT *DriverObject,
+            PUNICODE_STRING RegistryPath
+            );
+
+        typedef
+        VOID
+        DRIVER_UNLOAD(
+            struct _DRIVER_OBJECT *DriverObject
+            );
+
+        typedef
+        NTSTATUS
+        DRIVER_ADD_DEVICE(
+            struct _DRIVER_OBJECT *DriverObject,
+            struct _DEVICE_OBJECT *PhysicalDeviceObject
+            );
+
+        typedef
+        NTSTATUS
+        DRIVER_DISPATCH(
+            struct _DEVICE_OBJECT *DeviceObject,
+            struct _IRP *Irp
+            );
+
+        typedef
+        VOID
+        DRIVER_CANCEL(
+            struct _DEVICE_OBJECT *DeviceObject,
+            struct _IRP *Irp
+            );
+
+        typedef
+        BOOLEAN
+        KSERVICE_ROUTINE(
+            struct _KINTERRUPT *Interrupt,
+            PVOID ServiceContext
+            );
+
+        typedef
+        VOID
+        KDEFERRED_ROUTINE(
+            struct _KDPC *Dpc,
+            PVOID DeferredContext,
+            PVOID SystemArgument1,
+            PVOID SystemArgument2
+            );
+
+        typedef
+        BOOLEAN
+        KSYNCHRONIZE_ROUTINE (
+            PVOID SynchronizeContext
+            );
+
+        typedef
+        NTSTATUS
+        IO_COMPLETION_ROUTINE (
+            PDEVICE_OBJECT DeviceObject,
+            PIRP Irp,
+            PVOID Context
+            );
+
+        typedef
+        VOID
+        IO_WORKITEM_ROUTINE (
+            PDEVICE_OBJECT DeviceObject,
+            PVOID Context
+            );
+
+        typedef
+        VOID
+        REQUEST_POWER_COMPLETE (
+            PDEVICE_OBJECT DeviceObject,
+            UCHAR MinorFunction,
+            POWER_STATE PowerState,
+            PVOID Context,
+            PIO_STATUS_BLOCK IoStatus
+            );
+
+    #endif
+#endif
+
+
+
+/*******************************************
+ *        DOS Type Definitions
+ ******************************************/
+#if defined(PLX_DOS)
+    typedef signed char           S8;
+    typedef unsigned char         U8;
+    typedef signed short          S16;
+    typedef unsigned short        U16;
+    typedef signed long           S32;
+    typedef unsigned long         U32;
+    typedef signed long long      S64;
+    typedef unsigned long long    U64;
+    typedef S32                   PLX_INT_PTR;        // For 32/64-bit code compatability
+    typedef U32                   PLX_UINT_PTR;
+    typedef unsigned long         HANDLE;
+    typedef HANDLE                PLX_DRIVER_HANDLE;
+    #define INVALID_HANDLE_VALUE  0
+
+    #if !defined(_far)
+        #define _far
+    #endif
+#endif
+
+
+
+/*******************************************
+ *    Volatile Basic Type Definitions
+ ******************************************/
+typedef volatile S8           VS8;
+typedef volatile U8           VU8;
+typedef volatile S16          VS16;
+typedef volatile U16          VU16;
+typedef volatile S32          VS32;
+typedef volatile U32          VU32;
+typedef volatile S64          VS64;
+typedef volatile U64          VU64;
+
+
+
+/*******************************************
+ * Definitions used for ACPI & ECAM probe
+ ******************************************/
+// Used to scan ROM for services
+#define BIOS_MEM_START                  0x000E0000
+#define BIOS_MEM_END                    0x00100000
+
+// ACPI probe states
+#define ACPI_PCIE_NOT_PROBED            0
+#define ACPI_PCIE_BYPASS_OS_OK          1
+#define ACPI_PCIE_DEFAULT_TO_OS         2
+#define ACPI_PCIE_ALWAYS_USE_OS         3
+
+// ECAM probe definitions
+#define ECAM_PROBE_ADDR_MIN             0x80000000
+#define ECAM_PROBE_ADDR_MAX             0xFC000000
+#define ECAM_PROBE_ADDR_INCR            0x01000000
+#define ECAM_PROBE_ADDR_DEFAULT_START   0xC0000000
+#define ECAM_PROBE_ADDR_DEFAULT_END     0xFC000000
+
+// Number of PCI registers to compare
+#define ECAM_PROBE_REG_CMP_COUNT        4
+
+// ECAM address offset
+#define ECAM_DEVICE_REG_OFFSET( bus, dev, fn, off ) \
+               (U32)( ( (bus) << 20) | \
+                      ( (dev) << 15) | \
+                      ( (fn)  << 12) | \
+                      ( (off) <<  0) )
+
+// ACPI RSDT v1.0 structure
+typedef struct _ACPI_RSDT_v1_0
+{
+    U32 Signature;
+    U32 Length;
+    U8  Revision;
+    U8  Oem_Id[6];
+    U8  Oem_Table_Id[8];
+    U32 Oem_Revision;
+    U32 Creator_Id;
+    U32 Creator_Revision;
+} ACPI_RSDT_v1_0;
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/PexApi.h b/Plxlibrary/PexApi.h
new file mode 100755
index 0000000..8fc5fe1
--- /dev/null
+++ b/Plxlibrary/PexApi.h
@@ -0,0 +1,745 @@
+#ifndef __PEX_API_H
+#define __PEX_API_H
+
+/*******************************************************************************
+ * Copyright 2013-2019 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *     PexApi.h
+ *
+ * Description:
+ *
+ *     This file contains all the PLX API function prototypes
+ *
+ * Revision:
+ *
+ *     09-01-19 : PCI/PCIe SDK v8.10
+ *
+ ******************************************************************************/
+
+
+#include "PlxTypes.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/******************************************
+ *             Definitions
+ ******************************************/
+// DLL support
+#ifndef EXPORT
+    #if defined(PLX_MSWINDOWS)
+        #define EXPORT __declspec(dllexport)
+    #else
+        #define EXPORT
+    #endif
+#endif
+
+
+
+
+/******************************************
+ *      Device Selection Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_DeviceOpen(
+    PLX_DEVICE_KEY    *pKey,
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DeviceClose(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DeviceFind(
+    PLX_DEVICE_KEY *pKey,
+    U16             DeviceNumber
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DeviceFindEx(
+    PLX_DEVICE_KEY *pKey,
+    U16             DeviceNumber,
+    PLX_API_MODE    ApiMode,
+    PLX_MODE_PROP  *pModeProp
+    );
+
+PLX_STATUS EXPORT
+PlxPci_I2cGetPorts(
+    PLX_API_MODE  ApiMode,
+    U32          *pI2cPorts
+    );
+
+
+/******************************************
+ *    Query for Information Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_ApiVersion(
+    U8 *pVersionMajor,
+    U8 *pVersionMinor,
+    U8 *pVersionRevision
+    );
+
+PLX_STATUS EXPORT
+PlxPci_I2cVersion(
+    U16          I2cPort,
+    PLX_VERSION *pVersion
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DriverVersion(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                *pVersionMajor,
+    U8                *pVersionMinor,
+    U8                *pVersionRevision
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DriverProperties(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_DRIVER_PROP   *pDriverProp
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DriverScheduleRescan(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+PLX_STATUS EXPORT
+PlxPci_ChipTypeGet(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16               *pChipType,
+    U8                *pRevision
+    );
+
+PLX_STATUS EXPORT
+PlxPci_ChipTypeSet(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                ChipType,
+    U8                 Revision
+    );
+
+PLX_STATUS EXPORT
+PlxPci_ChipGetPortMask(
+    U32            ChipID,
+    U8             Revision,
+    PEX_CHIP_FEAT *PtrFeat
+    );
+
+PLX_STATUS EXPORT
+PlxPci_GetPortProperties(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PORT_PROP     *pPortProp
+    );
+
+
+/******************************************
+ *        Device Control Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_DeviceReset(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+
+/******************************************
+ *        Register Access Functions
+ *****************************************/
+U32 EXPORT
+PlxPci_PciRegisterRead(
+    U8          bus,
+    U8          slot,
+    U8          function,
+    U16         offset,
+    PLX_STATUS *pStatus
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PciRegisterWrite(
+    U8  bus,
+    U8  slot,
+    U8  function,
+    U16 offset,
+    U32 value
+    );
+
+U32 EXPORT
+PlxPci_PciRegisterReadFast(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                offset,
+    PLX_STATUS        *pStatus
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PciRegisterWriteFast(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                offset,
+    U32                value
+    );
+
+U32 EXPORT
+PlxPci_PciRegisterRead_BypassOS(
+    U8          bus,
+    U8          slot,
+    U8          function,
+    U16         offset,
+    PLX_STATUS *pStatus
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PciRegisterWrite_BypassOS(
+    U8  bus,
+    U8  slot,
+    U8  function,
+    U16 offset,
+    U32 value
+    );
+
+
+/******************************************
+ * Device-specific Register Functions
+ *****************************************/
+U32 EXPORT
+PlxPci_PlxRegisterRead(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    PLX_STATUS        *pStatus
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PlxRegisterWrite(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U32                value
+    );
+
+U32 EXPORT
+PlxPci_PlxMappedRegisterRead(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    PLX_STATUS        *pStatus
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PlxMappedRegisterWrite(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U32                value
+    );
+
+U32 EXPORT
+PlxPci_PlxMailboxRead(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                mailbox,
+    PLX_STATUS        *pStatus
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PlxMailboxWrite(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                mailbox,
+    U32                value
+    );
+
+
+/******************************************
+ *         PCI Mapping Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_PciBarProperties(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 BarIndex,
+    PLX_PCI_BAR_PROP  *pBarProperties
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PciBarMap(
+    PLX_DEVICE_OBJECT  *pDevice,
+    U8                  BarIndex,
+    VOID              **pVa
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PciBarUnmap(
+    PLX_DEVICE_OBJECT  *pDevice,
+    VOID              **pVa
+    );
+
+
+/******************************************
+ *   BAR I/O & Memory Access Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_IoPortRead(
+    PLX_DEVICE_OBJECT *pDevice,
+    U64                port,
+    VOID              *pBuffer,
+    U32                ByteCount,
+    PLX_ACCESS_TYPE    AccessType
+    );
+
+PLX_STATUS EXPORT
+PlxPci_IoPortWrite(
+    PLX_DEVICE_OBJECT *pDevice,
+    U64                port,
+    VOID              *pBuffer,
+    U32                ByteCount,
+    PLX_ACCESS_TYPE    AccessType
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PciBarSpaceRead(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 BarIndex,
+    U32                offset,
+    VOID              *pBuffer,
+    U32                ByteCount,
+    PLX_ACCESS_TYPE    AccessType,
+    BOOLEAN            bOffsetAsLocalAddr
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PciBarSpaceWrite(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 BarIndex,
+    U32                offset,
+    VOID              *pBuffer,
+    U32                ByteCount,
+    PLX_ACCESS_TYPE    AccessType,
+    BOOLEAN            bOffsetAsLocalAddr
+    );
+
+
+/******************************************
+ *       Physical Memory Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_PhysicalMemoryAllocate(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PHYSICAL_MEM  *pMemoryInfo,
+    BOOLEAN            bSmallerOk
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PhysicalMemoryFree(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PHYSICAL_MEM  *pMemoryInfo
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PhysicalMemoryMap(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PHYSICAL_MEM  *pMemoryInfo
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PhysicalMemoryUnmap(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PHYSICAL_MEM  *pMemoryInfo
+    );
+
+PLX_STATUS EXPORT
+PlxPci_CommonBufferProperties(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PHYSICAL_MEM  *pMemoryInfo
+    );
+
+PLX_STATUS EXPORT
+PlxPci_CommonBufferMap(
+    PLX_DEVICE_OBJECT  *pDevice,
+    VOID              **pVa
+    );
+
+PLX_STATUS EXPORT
+PlxPci_CommonBufferUnmap(
+    PLX_DEVICE_OBJECT  *pDevice,
+    VOID              **pVa
+    );
+
+
+/******************************************
+ *     Interrupt Support Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_InterruptEnable(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_INTERRUPT     *pPlxIntr
+    );
+
+PLX_STATUS EXPORT
+PlxPci_InterruptDisable(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_INTERRUPT     *pPlxIntr
+    );
+
+PLX_STATUS EXPORT
+PlxPci_NotificationRegisterFor(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_INTERRUPT     *pPlxIntr,
+    PLX_NOTIFY_OBJECT *pEvent
+    );
+
+PLX_STATUS EXPORT
+PlxPci_NotificationWait(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_NOTIFY_OBJECT *pEvent,
+    U64                Timeout_ms
+    );
+
+PLX_STATUS EXPORT
+PlxPci_NotificationStatus(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_NOTIFY_OBJECT *pEvent,
+    PLX_INTERRUPT     *pPlxIntr
+    );
+
+PLX_STATUS EXPORT
+PlxPci_NotificationCancel(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_NOTIFY_OBJECT *pEvent
+    );
+
+
+/******************************************
+ *     Serial EEPROM Access Functions
+ *****************************************/
+PLX_EEPROM_STATUS EXPORT
+PlxPci_EepromPresent(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_STATUS        *pStatus
+    );
+
+BOOLEAN EXPORT
+PlxPci_EepromProbe(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_STATUS        *pStatus
+    );
+
+PLX_STATUS EXPORT
+PlxPci_EepromGetAddressWidth(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                *pWidth
+    );
+
+PLX_STATUS EXPORT
+PlxPci_EepromSetAddressWidth(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 width
+    );
+
+PLX_STATUS EXPORT
+PlxPci_EepromCrcUpdate(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32               *pCrc,
+    BOOLEAN            bUpdateEeprom
+    );
+
+PLX_STATUS EXPORT
+PlxPci_EepromCrcGet(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32               *pCrc,
+    U8                *pCrcStatus
+    );
+
+PLX_STATUS EXPORT
+PlxPci_EepromReadByOffset(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U32               *pValue
+    );
+
+PLX_STATUS EXPORT
+PlxPci_EepromWriteByOffset(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U32                value
+    );
+
+PLX_STATUS EXPORT
+PlxPci_EepromReadByOffset_16(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U16               *pValue
+    );
+
+PLX_STATUS EXPORT
+PlxPci_EepromWriteByOffset_16(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U16                value
+    );
+
+
+/******************************************
+ *     SPI Flash Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_SpiFlashPropGet(
+    PLX_DEVICE_OBJECT *PtrDev,
+    U8                 ChipSel,
+    PEX_SPI_OBJ       *PtrSpi
+    );
+
+PLX_STATUS EXPORT
+PlxPci_SpiFlashErase(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi,
+    U32                StartOffset,
+    U8                 BoolWaitComplete
+    );
+
+PLX_STATUS EXPORT
+PlxPci_SpiFlashReadBuffer(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi,
+    U32                StartOffset,
+    U8                *PtrRxBuff,
+    U32                SizeRx
+    );
+
+U32 EXPORT
+PlxPci_SpiFlashReadByOffset(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi,
+    U32                Offset,
+    PLX_STATUS        *PtrStatus
+    );
+
+PLX_STATUS EXPORT
+PlxPci_SpiFlashWriteBuffer(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi,
+    U32                StartOffset,
+    U8                *PtrTxBuff,
+    U32                SizeTx
+    );
+
+PLX_STATUS EXPORT
+PlxPci_SpiFlashWriteByOffset(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi,
+    U32                Offset,
+    U32                Data
+    );
+
+PLX_STATUS EXPORT
+PlxPci_SpiFlashGetStatus(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi
+    );
+
+
+/******************************************
+ *          PLX VPD Functions
+ *****************************************/
+U32 EXPORT 
+PlxPci_VpdRead(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                offset,
+    PLX_STATUS        *pStatus
+    );
+
+PLX_STATUS EXPORT
+PlxPci_VpdWrite(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                offset,
+    U32                value
+    );
+
+
+/******************************************
+ *            DMA Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_DmaChannelOpen(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 channel,
+    PLX_DMA_PROP      *pDmaProp
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DmaGetProperties(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 channel,
+    PLX_DMA_PROP      *pDmaProp
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DmaSetProperties(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 channel,
+    PLX_DMA_PROP      *pDmaProp
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DmaControl(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 channel,
+    PLX_DMA_COMMAND    command
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DmaStatus(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 channel
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DmaTransferBlock(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 channel,
+    PLX_DMA_PARAMS    *pDmaParams,
+    U64                Timeout_ms
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DmaTransferUserBuffer(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 channel,
+    PLX_DMA_PARAMS    *pDmaParams,
+    U64                Timeout_ms
+    );
+
+PLX_STATUS EXPORT
+PlxPci_DmaChannelClose(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 channel
+    );
+
+
+/******************************************
+ *   Performance Monitoring Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_PerformanceInitializeProperties(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PERF_PROP     *pPerfObject
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PerformanceMonitorControl(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PERF_CMD       command
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PerformanceResetCounters(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PERF_PROP     *pPerfProps,
+    U8                 NumOfObjects
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PerformanceGetCounters(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PERF_PROP     *pPerfProps,
+    U8                 NumOfObjects
+    );
+
+PLX_STATUS EXPORT
+PlxPci_PerformanceCalcStatistics(
+    PLX_PERF_PROP  *pPerfProp,
+    PLX_PERF_STATS *pPerfStats,
+    U32             ElapsedTime_ms
+    );
+
+
+/******************************************
+ *    Multi-Host Switch Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_MH_GetProperties(
+    PLX_DEVICE_OBJECT   *pDevice,
+    PLX_MULTI_HOST_PROP *pMHProp
+    );
+
+PLX_STATUS EXPORT
+PlxPci_MH_MigratePorts(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                VS_Source,
+    U16                VS_Dest,
+    U32                DsPortMask,
+    BOOLEAN            bResetSrc
+    );
+
+
+/******************************************
+ *  PLX Non-Transparent Port Functions
+ *****************************************/
+PLX_STATUS EXPORT
+PlxPci_Nt_ReqIdProbe(
+    PLX_DEVICE_OBJECT *pDevice,
+    BOOLEAN            bRead,
+    U16               *pReqId
+    );
+
+PLX_STATUS EXPORT
+PlxPci_Nt_LutProperties(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                LutIndex,
+    U16               *pReqId,
+    U32               *pFlags,
+    BOOLEAN           *pbEnabled
+    );
+
+PLX_STATUS EXPORT
+PlxPci_Nt_LutAdd(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16               *pLutIndex,
+    U16                ReqId,
+    U32                flags
+    );
+
+PLX_STATUS EXPORT
+PlxPci_Nt_LutDisable(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                LutIndex
+    );
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/Plx.h b/Plxlibrary/Plx.h
new file mode 100755
index 0000000..7701e24
--- /dev/null
+++ b/Plxlibrary/Plx.h
@@ -0,0 +1,122 @@
+#ifndef __PLX_H
+#define __PLX_H
+
+/*******************************************************************************
+ * Copyright 2013-2020 Broadcom, Inc.
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      Plx.h
+ *
+ * Description:
+ *
+ *      This file contains definitions that are common to all PCI SDK code
+ *
+ * Revision:
+ *
+ *     11-17-20 : PCI/PCIe SDK v8.23
+ *
+ ******************************************************************************/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+/**********************************************
+*               Definitions
+**********************************************/
+// SDK Version information
+#define PLX_SDK_VERSION_MAJOR            8
+#define PLX_SDK_VERSION_MINOR            23
+#define PLX_SDK_VERSION_STRING           "8.23"
+#define PLX_SDK_PRODUCT_NAME_STRING      "Broadcom PCI/PCIe SDK"
+#define PLX_SDK_COMPANY_NAME_STRING      "Broadcom Ltd."
+#define PLX_SDK_COPYRIGHT_STRING         "\251 Broadcom 2020"
+
+// Device object validity codes
+#define PLX_TAG_VALID                    0x5F504C58     // "_PLX" in Hex
+#define PLX_TAG_INVALID                  0x564F4944     // "VOID" in Hex
+#define ObjectValidate(pObj)             ((pObj)->IsValidTag = PLX_TAG_VALID)
+#define ObjectInvalidate(pObj)           ((pObj)->IsValidTag = PLX_TAG_INVALID)
+#define IsObjectValid(pObj)              ((pObj)->IsValidTag == PLX_TAG_VALID)
+
+// Used for locating PCI devices
+#define PCI_FIELD_IGNORE                 (-1)
+
+// Used for VPD accesses
+#define VPD_COMMAND_MAX_RETRIES          5         // Max number VPD command re-issues
+#define VPD_STATUS_MAX_POLL              10        // Max number of times to read VPD status
+#define VPD_STATUS_POLL_DELAY            5         // Delay between polling VPD status (Milliseconds)
+
+// Define a large value for a signal to the driver
+#define FIND_AMOUNT_MATCHED              80001
+
+// Max ports
+#define PEX_MAX_PORT                     128
+#define PEX_PORT_REGS_SIZE               (4 * 1024)
+
+// Used for performance counter calculations
+#define PERF_MAX_PORTS                   96                             // Max # ports in a switch
+#define PERF_COUNTERS_PER_PORT           14                             // Number of counters per port
+#define PERF_TLP_OH_DW                   2                              // Overhead DW per TLP
+#define PERF_TLP_DW                      (3 + PERF_TLP_OH_DW)           // DW per TLP
+#define PERF_TLP_SIZE                    (PERF_TLP_DW * sizeof(U32))    // TLP header bytes with overhead
+#define PERF_TLP_SIZE_NO_OH              (3 * sizeof(U32))              // TLP header bytes w/o overhead
+#define PERF_DLLP_SIZE                   (2 * sizeof(U32))              // Bytes per DLLP
+#define PERF_MAX_BPS_GEN_1_0             ((U64)250000000)               // 250 MB/s (2.5 Gbps)
+#define PERF_MAX_BPS_GEN_2_0             ((U64)500000000)               // 500 MB/s (5 Gbps)
+#define PERF_MAX_BPS_GEN_3_0             ((U64)1000000000)              //   1 GB/s (8 Gbps)
+#define PERF_MAX_BPS_GEN_4_0             ((U64)2000000000)              //   2 GB/s (16 Gbps)
+
+// Endian swap macros
+#define EndianSwap32(value)              ( ((((value) >>  0) & 0xff) << 24) | \
+                                           ((((value) >>  8) & 0xff) << 16) | \
+                                           ((((value) >> 16) & 0xff) <<  8) | \
+                                           ((((value) >> 24) & 0xff) <<  0) )
+
+#define EndianSwap16(value)              ( ((((value) >>  0) & 0xffff) << 16) | \
+                                           ((((value) >> 16) & 0xffff) <<  0) )
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/PlxApi.h b/Plxlibrary/PlxApi.h
new file mode 100755
index 0000000..03106d6
--- /dev/null
+++ b/Plxlibrary/PlxApi.h
@@ -0,0 +1,73 @@
+#ifndef __PLX_API_H
+#define __PLX_API_H
+
+/*******************************************************************************
+ * Copyright 2013-2015 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      PlxApi.h
+ *
+ * Description:
+ *
+ *      The main PLX API include file
+ *
+ * Revision:
+ *
+ *      02-01-07 : PLX SDK v5.00
+ *
+ ******************************************************************************/
+
+
+
+
+/**********************************************
+*          Verify Required Definitions
+**********************************************/
+#include "PlxDefCk.h"
+
+
+
+
+/**********************************************
+*              Include Files
+**********************************************/
+#include "Plx.h"
+#include "PlxTypes.h"
+#include "PexApi.h"
+
+
+
+#endif
diff --git a/Plxlibrary/PlxApiDebug.h b/Plxlibrary/PlxApiDebug.h
new file mode 100755
index 0000000..aef7781
--- /dev/null
+++ b/Plxlibrary/PlxApiDebug.h
@@ -0,0 +1,150 @@
+#ifndef __PLX_API_DEBUG_H
+#define __PLX_API_DEBUG_H
+
+/*******************************************************************************
+ * Copyright 2013-2019 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *     PlxApiDebug.h
+ *
+ * Description:
+ *
+ *     PLX API debug support functions header
+ *
+ * Revision:
+ *
+ *     09-01-19: PLX SDK v8.10
+ *
+ ******************************************************************************/
+
+
+#include <stdio.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/******************************************
+ *             Definitions
+ *****************************************/
+// Ensure debug is enabled for debug builds
+#if defined(DEBUG) || defined(_DEBUG)
+    #define PLX_DEBUG
+#endif
+
+// Remove any existing definitions of debug macros
+#if defined(DebugPrintf)
+    #undef DebugPrintf
+    #undef DebugPrintf_Cont
+    #undef InfoPrintf
+    #undef InfoPrintf_Cont
+    #undef ErrorPrintf
+    #undef ErrorPrintf_Cont
+    #undef _PlxDbgFunc
+    #undef _PlxDbgOut
+    #undef _Debug_Print_Macro
+#endif
+
+
+// Set log data destination
+#if defined(WIN32)
+    #define PLX_DBG_DEST_DEBUGGER           // Default Win DLL to debugger
+#elif defined(PLX_LINUX)
+    #define PLX_DBG_DEST_CONSOLE            // Default Linux API to console
+#elif defined(PLX_DOS)
+    #define PLX_DBG_DEST_FILE               // Default DOS API to file
+#else
+    #define PLX_DBG_DEST_CONSOLE            // Default to console
+#endif
+
+
+// Debug definitions
+#if defined(PLX_DBG_DEST_FILE)
+    #define _PlxDbgFunc                     PlxApi_DebugPrintf
+    #define PLX_LOG_FILE                    "PlxApi.Log"        // Log file for debug output
+#elif defined(PLX_DBG_DEST_DEBUGGER)
+    #if defined(WIN32)
+        #define _PlxDbgFunc                 PlxApi_DebugPrintf
+        #define _PlxDbgOut                  OutputDebugStringA
+    #endif
+#elif defined(PLX_DBG_DEST_CONSOLE)
+    #define _PlxDbgFunc                     printf
+    #define _PlxDbgOut                      puts
+#endif
+
+#if defined(PLX_DEBUG)
+    #define DebugPrintf(arg)                _Debug_Print_Macro(arg)
+    #define DebugPrintf_Cont(arg)           _PlxDbgFunc arg
+    #define ErrorPrintf(arg)                _Debug_Print_Macro(arg)
+    #define ErrorPrintf_Cont(arg)           _PlxDbgFunc arg
+#else
+    #define DebugPrintf(arg)                do { } while(0)
+    #define DebugPrintf_Cont(arg)           do { } while(0)
+    #define ErrorPrintf(arg)                do { } while(0)
+    #define ErrorPrintf_Cont(arg)           do { } while(0)
+#endif
+#define InfoPrintf(arg)                     _Debug_Print_Macro(arg)
+#define InfoPrintf_Cont(arg)                _PlxDbgFunc arg
+
+#define _Debug_Print_Macro(arg)  \
+    do                           \
+    {                            \
+        _PlxDbgFunc("PlxApi: "); \
+        _PlxDbgFunc arg;         \
+    }                            \
+    while (0)
+
+
+
+/******************************************
+ *             Functions
+ *****************************************/
+extern void
+PlxApi_DebugPrintf(
+    const char *format,
+    ...
+    );
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/PlxApiDirect.h b/Plxlibrary/PlxApiDirect.h
new file mode 100755
index 0000000..a3f4a28
--- /dev/null
+++ b/Plxlibrary/PlxApiDirect.h
@@ -0,0 +1,346 @@
+#ifndef __PLX_API_DIRECT_H
+#define __PLX_API_DIRECT_H
+
+/*******************************************************************************
+ * Copyright 2013-2019 Broadcom Inc
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *     PlxApiDirect.h
+ *
+ * Description:
+ *
+ *     PLX API function prototypes at API level for direct connect interfaces
+ *
+ * Revision:
+ *
+ *     09-01-19: PCI/PCIe SDK v8.10
+ *
+ ******************************************************************************/
+
+
+#include "PlxTypes.h"
+#if defined(PLX_LINUX)
+    #include <pthread.h>    // For mutex support
+    #include <unistd.h>     // For usleep()
+#elif defined(PLX_DOS)
+    #include <unistd.h>     // For usleep()
+#endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+/******************************************
+ *             Definitions
+ ******************************************/
+
+// For displaying connection mode in debug statements
+#define DbgGetApiModeStr( pDev ) \
+        ( ((pDev)->Key.ApiMode == PLX_API_MODE_PCI) ? "PCI" : \
+          ((pDev)->Key.ApiMode == PLX_API_MODE_SDB) ? "SDB" : \
+          ((pDev)->Key.ApiMode == PLX_API_MODE_I2C_AARDVARK) ? "I2C" : \
+          ((pDev)->Key.ApiMode == PLX_API_MODE_MDIO_SPLICE) ? "MDIO" : \
+          "??" )
+
+// Addresses used for probe, register, & flash accesses
+#define ATLAS_REGS_AXI_CCR_BASE_ADDR        0xFFF00000
+#define ATLAS_REGS_AXI_BASE_ADDR            0x60800000
+#define ATLAS_REGS_AXI_MAVERICK_BASE_ADDR   0x60000000
+#define _REG_CCR(offset)                    (ATLAS_REGS_AXI_CCR_BASE_ADDR + (offset))
+
+// Addresses dependent upon access mode
+#define ATLAS_REGS_PCI_PBAM_BASE_ADDR       0x001C0000
+#define ATLAS_REGS_AXI_PBAM_BASE_ADDR       0x2A0C0000
+#define ATLAS_SPI_CS0_AXI_BASE_ADDR         0x10000000
+#define ATLAS_SPI_CS0_PCI_BASE_ADDR         0x00300000
+
+// Atlas PEX registers start offset
+#if !defined(ATLAS_PEX_REGS_BASE_OFFSET)
+    #define ATLAS_PEX_REGS_BASE_OFFSET      ATLAS_REGS_AXI_BASE_ADDR
+#endif
+
+// CCR registers
+#define ATLAS_REG_CCR_DEV_ID                _REG_CCR( 0x0 )
+#define ATLAS_REG_CCR_PCIE_SW_MODE          _REG_CCR( 0xB0 )
+#define ATLAS_REG_CCR_PORT_TYPE0            _REG_CCR( 0x120 )
+#define ATLAS_REG_CCR_PCIE_CONFIG           _REG_CCR( 0x170 )
+
+// Chip registers
+#define ATLAS_REG_PORT_CLOCK_EN_0           0x30C    // Port clock enable for 0-31
+#define ATLAS_REG_PORT_CLOCK_EN_1           0x310    // Port clock enable for 32-63
+#define ATLAS_REG_PORT_CLOCK_EN_2           0x314    // Port clock enable for 64-95
+#define ATLAS_REG_VS0_UPSTREAM              0x360    // Port upstream setting
+#define ATLAS_REG_IDX_AXI_ADDR              0x1F0100 // Index access AXI address
+#define ATLAS_REG_IDX_AXI_DATA              0x1F0104 // Index access data
+#define ATLAS_REG_IDX_AXI_CTRL              0x1F0108 // Index access control
+
+// Per port registers
+#define ATLAS_OFF_PORT_CAP_BUS              0x97C    // Port captured bus
+
+// PEX CSR index method control
+#define PEX_IDX_CTRL_CMD_READ               (1 << 1) // READ command
+#define PEX_IDX_CTRL_CMD_WRITE              (1 << 0) // WRITE command
+#define PEX_IDX_CTRL_READ_VALID             (1 << 3) // Indicates READ completed
+#define PEX_IDX_CTRL_BUSY                   (1 << 2) // Indicates operation pending
+
+// Maverick
+#define ATLAS_REG_MAV_HOST_DIAG             0x08     // Maverick host diag reg
+#define ATLAS_MAV_HOST_DIAG_CPU_RESET_MASK  (1 << 1) // Hold CPU in reset
+
+
+
+
+/**********************************************
+ *           Portability Functions
+ *********************************************/
+#if defined(PLX_MSWINDOWS)
+
+    #define Plx_sleep                       Sleep
+
+#elif defined(PLX_LINUX)
+
+    #define Plx_sleep(arg)                  usleep((arg) * 1000)
+
+    #define CRITICAL_SECTION                pthread_mutex_t
+    #define InitializeCriticalSection(pCS)  pthread_mutex_init   ( (pCS), NULL )
+    #define DeleteCriticalSection(pCS)      pthread_mutex_destroy( (pCS) )
+    #define EnterCriticalSection(pCS)       pthread_mutex_lock   ( (pCS) )
+    #define LeaveCriticalSection(pCS)       pthread_mutex_unlock ( (pCS) )
+
+    #define InterlockedIncrement( pVal )    ++(*(pVal))
+    #define InterlockedDecrement( pVal )    --(*(pVal))
+
+#elif defined(PLX_DOS)
+
+    #define Plx_sleep(arg)                  usleep((arg) * 1000)
+
+#endif
+
+#if !defined(PLX_8000_REG_READ)
+    // Macros for PLX chip register access
+    #define PLX_PCI_REG_READ(pDevice, offset, pValue)   *(pValue) = PlxDir_PlxRegRead( (pDevice), (U16)(offset), NULL )
+    #define PLX_PCI_REG_WRITE(pDevice, offset, value)   PlxDir_PlxRegWrite( (pDevice), (U16)(offset), (value) )
+    #define PLX_8000_REG_READ(pDevice, offset)          PlxDir_PlxMappedRegRead( (pDevice), (offset), NULL )
+    #define PLX_8000_REG_WRITE(pDevice, offset, value)  PlxDir_PlxMappedRegWrite( (pDevice), (offset), (value) )
+#endif
+
+
+
+
+/******************************************
+ *    Query for Information Functions
+ *****************************************/
+PLX_STATUS
+PlxDir_ChipTypeGet(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16               *pChipType,
+    U8                *pRevision
+    );
+
+PLX_STATUS
+PlxDir_ChipTypeSet(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                ChipType,
+    U8                 Revision
+    );
+
+PLX_STATUS
+PlxDir_GetPortProperties(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PORT_PROP     *pPortProp
+    );
+
+
+/******************************************
+ *           PCI BAR Functions
+ *****************************************/
+PLX_STATUS
+PlxDir_PciBarProperties(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 BarIndex,
+    PLX_PCI_BAR_PROP  *pBarProperties
+    );
+
+
+/******************************************
+ *     SPI Flash Functions
+ *****************************************/
+PLX_STATUS
+PlxDir_SpiFlashPropGet(
+    PLX_DEVICE_OBJECT *pDevice,
+    U8                 ChipSel,
+    PEX_SPI_OBJ       *PtrSpi
+    );
+
+PLX_STATUS
+PlxDir_SpiFlashErase(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi,
+    U32                StartOffset,
+    U8                 BoolWaitComplete
+    );
+
+PLX_STATUS
+PlxDir_SpiFlashReadBuffer(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi,
+    U32                StartOffset,
+    U8                *PtrRxBuff,
+    U32                SizeRx
+    );
+
+PLX_STATUS
+PlxDir_SpiFlashWriteBuffer(
+    PLX_DEVICE_OBJECT *PtrDevice,
+    PEX_SPI_OBJ       *PtrSpi,
+    U32                StartOffset,
+    U8                *PtrTxBuff,
+    U32                SizeTx
+    );
+
+PLX_STATUS
+PlxDir_SpiFlashGetStatus(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi
+    );
+
+
+/******************************************
+ *   Performance Monitor Functions
+ *****************************************/
+PLX_STATUS
+PlxDir_PerformanceInitializeProperties(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PERF_PROP     *pPerfObject
+    );
+
+PLX_STATUS
+PlxDir_PerformanceMonitorControl(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PERF_CMD       command
+    );
+
+PLX_STATUS
+PlxDir_PerformanceResetCounters(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+PLX_STATUS
+PlxDir_PerformanceGetCounters(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_PERF_PROP     *pPerfProps,
+    U8                 NumOfObjects
+    );
+
+
+/******************************************
+ *      Private Support Functions
+ *****************************************/
+U16
+PlxDir_PciFindCapability(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                CapID,
+    U8                 bPCIeCap,
+    U8                 InstanceNum
+    );
+
+BOOLEAN
+PlxDir_ChipTypeDetect(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+VOID
+PlxDir_ChipRevisionDetect(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+PLX_STATUS
+PlxDir_ChipFilterDisabledPorts(
+    PLX_DEVICE_OBJECT *pDevice,
+    PEX_CHIP_FEAT     *PtrFeat
+    );
+
+PLX_STATUS
+PlxDir_ProbeSwitch(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_DEVICE_KEY    *pKey,
+    U16                DeviceNumber,
+    U16               *pNumMatched
+    );
+
+
+/******************************************
+ *  Private Register Dispatch Functions
+ *****************************************/
+U32
+PlxDir_PlxRegRead(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                offset,
+    PLX_STATUS        *pStatus
+    );
+
+PLX_STATUS
+PlxDir_PlxRegWrite(
+    PLX_DEVICE_OBJECT *pDevice,
+    U16                offset,
+    U32                value
+    );
+
+U32
+PlxDir_PlxMappedRegRead(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    PLX_STATUS        *pStatus
+    );
+
+PLX_STATUS
+PlxDir_PlxMappedRegWrite(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U32                value
+    );
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/PlxDefCk.h b/Plxlibrary/PlxDefCk.h
new file mode 100755
index 0000000..06cd1fc
--- /dev/null
+++ b/Plxlibrary/PlxDefCk.h
@@ -0,0 +1,84 @@
+/*******************************************************************************
+ * Copyright 2013-2015 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      PlxDefCk.h
+ *
+ * Description:
+ *
+ *      Verifies definitions required by the PLX API
+ *
+ * Revision:
+ *
+ *      05-01-12 : PLX SDK v7.00
+ *
+ ******************************************************************************/
+
+
+
+
+/**********************************************
+*       Automatic selection for Windows
+**********************************************/
+#if defined(_WIN32) || defined(_WIN64)
+    #if !defined(PLX_LITTLE_ENDIAN) && !defined(PLX_BIG_ENDIAN)
+        #define PLX_LITTLE_ENDIAN
+    #endif
+
+    #if defined(_WIN64)
+        #define PLX_CPU_BITS    64
+    #else
+        #define PLX_CPU_BITS    32
+    #endif
+
+    #define PLX_MSWINDOWS
+#endif
+
+
+#if defined(PLX_LINUX)
+    #if !defined(PLX_LITTLE_ENDIAN) && !defined(PLX_BIG_ENDIAN)
+        #define PLX_LITTLE_ENDIAN
+    #endif
+#endif
+
+
+
+/**********************************************
+*               Error Checks
+**********************************************/
+#if !defined(PLX_LITTLE_ENDIAN) && !defined(PLX_BIG_ENDIAN)
+    #error ERROR: Either PLX_LITTLE_ENDIAN or PLX_BIG_ENDIAN must be defined.
+#endif
diff --git a/Plxlibrary/PlxInit.h b/Plxlibrary/PlxInit.h
new file mode 100755
index 0000000..0b98bc9
--- /dev/null
+++ b/Plxlibrary/PlxInit.h
@@ -0,0 +1,103 @@
+#ifndef PLXINIT_H
+#define PLXINIT_H
+
+/*******************************************************************************
+ * Copyright 2013-2015 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      PlxInit.h
+ *
+ * Description:
+ *
+ *      Header file for the PlxInit.c module
+ *
+ * Revision History:
+ *
+ *      12-01-07 : PLX SDK v5.20
+ *
+ ******************************************************************************/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include "PlxTypes.h"
+
+
+
+
+/******************************
+*        Definitions
+******************************/
+#define MAX_DEVICES_TO_LIST        100
+
+typedef struct _API_ERRORS
+{
+    PLX_STATUS  code;
+    char       *text;
+} API_ERRORS;
+
+
+
+
+/********************************************************************************
+*        Functions
+*********************************************************************************/
+S16
+SelectDevice(
+    PLX_DEVICE_KEY *pKey
+    );
+
+char*
+PlxSdkErrorText(
+    PLX_STATUS code
+    );
+
+void
+PlxSdkErrorDisplay(
+    PLX_STATUS code
+    );
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/PlxIoctl.h b/Plxlibrary/PlxIoctl.h
new file mode 100755
index 0000000..a49cded
--- /dev/null
+++ b/Plxlibrary/PlxIoctl.h
@@ -0,0 +1,293 @@
+#ifndef __PLX_IOCTL_H
+#define __PLX_IOCTL_H
+
+/*******************************************************************************
+ * Copyright 2013-2016 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      PlxIoctl.h
+ *
+ * Description:
+ *
+ *      This file contains the common I/O Control messages shared between
+ *      the driver and the PCI API.
+ *
+ * Revision History:
+ *
+ *      09-01-19 : PCI/PCIe SDK v8.10
+ *
+ ******************************************************************************/
+
+
+#include "PlxTypes.h"
+
+#if defined(PLX_MSWINDOWS) && !defined(PLX_DRIVER)
+    #include <winioctl.h>
+#elif defined(PLX_LINUX)
+    #include <fcntl.h>
+    #include <unistd.h>
+    #include <sys/ioctl.h>
+#endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+// Set structure packing for consistentcy in kernel/user levels & save current
+#pragma pack( push, 4 )
+
+
+
+
+// Used to pass IOCTL arguments down to the driver
+typedef struct _PLX_PARAMS
+{
+    PLX_STATUS     ReturnCode;      // API status code
+    PLX_DEVICE_KEY Key;             // Device key information
+    U64            value[3];        // Generic storage for parameters
+    union
+    {
+        U64                 ExData[5];
+        PLX_INTERRUPT       PlxIntr;
+        PLX_PHYSICAL_MEM    PciMemory;
+        PLX_PORT_PROP       PortProp;
+        PLX_PCI_BAR_PROP    BarProp;
+        PLX_DMA_PROP        DmaProp;
+        PLX_DMA_PARAMS      TxParams;
+        PLX_DRIVER_PROP     DriverProp;
+        PLX_MULTI_HOST_PROP MH_Prop;
+        PEX_SPI_OBJ         SpiProp;
+    } u;
+} PLX_PARAMS;
+
+
+#if defined(PLX_MSWINDOWS)
+    /**********************************************************
+     * Note: Codes 0-2047 (0-7FFh) are reserved by Microsoft
+     *       Coded 2048-4095 (800h-FFFh) are reserved for OEMs
+     *********************************************************/
+    #define PLX_IOCTL_CODE_BASE      0x800
+    #define IOCTL_MSG( code )        CTL_CODE(                \
+                                         FILE_DEVICE_UNKNOWN, \
+                                         code,                \
+                                         METHOD_BUFFERED,     \
+                                         FILE_ANY_ACCESS      \
+                                         )
+
+#elif defined(PLX_LINUX) || defined(PLX_LINUX_DRIVER)
+
+    #define PLX_IOCTL_CODE_BASE      0x0
+    #define PLX_MAGIC                'P'
+    #define IOCTL_MSG( code )        _IOWR(         \
+                                         PLX_MAGIC, \
+                                         code,      \
+                                         PLX_PARAMS \
+                                         )
+
+#elif defined(PLX_DOS)
+
+    #define PLX_IOCTL_CODE_BASE      0x0
+    #define IOCTL_MSG( code )        code
+
+#endif
+
+
+typedef enum _DRIVER_MSGS
+{
+    MSG_DRIVER_VERSION = PLX_IOCTL_CODE_BASE,
+    MSG_DRIVER_PROPERTIES,
+    MSG_DRIVER_SCHEDULE_RESCAN,
+    MSG_CHIP_TYPE_GET,
+    MSG_CHIP_TYPE_SET,
+    MSG_GET_PORT_PROPERTIES,
+    MSG_PCI_DEVICE_RESET,
+    MSG_PCI_DEVICE_FIND,
+    MSG_PCI_BAR_PROPERTIES,
+    MSG_PCI_BAR_MAP,
+    MSG_PCI_BAR_UNMAP,
+    MSG_PCI_REGISTER_READ,
+    MSG_PCI_REGISTER_WRITE,
+    MSG_PCI_REG_READ_BYPASS_OS,
+    MSG_PCI_REG_WRITE_BYPASS_OS,
+    MSG_REGISTER_READ,
+    MSG_REGISTER_WRITE,
+    MSG_MAPPED_REGISTER_READ,
+    MSG_MAPPED_REGISTER_WRITE,
+    MSG_PHYSICAL_MEM_ALLOCATE,
+    MSG_PHYSICAL_MEM_FREE,
+    MSG_PHYSICAL_MEM_MAP,
+    MSG_PHYSICAL_MEM_UNMAP,
+    MSG_COMMON_BUFFER_PROPERTIES,
+    MSG_IO_PORT_READ,
+    MSG_IO_PORT_WRITE,
+    MSG_PCI_BAR_SPACE_READ,
+    MSG_PCI_BAR_SPACE_WRITE,
+    MSG_VPD_READ,
+    MSG_VPD_WRITE,
+    MSG_EEPROM_PRESENT,
+    MSG_EEPROM_PROBE,
+    MSG_EEPROM_GET_ADDRESS_WIDTH,
+    MSG_EEPROM_SET_ADDRESS_WIDTH,
+    MSG_EEPROM_CRC_GET,
+    MSG_EEPROM_CRC_UPDATE,
+    MSG_EEPROM_READ_BY_OFFSET,
+    MSG_EEPROM_WRITE_BY_OFFSET,
+    MSG_EEPROM_READ_BY_OFFSET_16,
+    MSG_EEPROM_WRITE_BY_OFFSET_16,
+    MSG_MAILBOX_READ,
+    MSG_MAILBOX_WRITE,
+    MSG_INTR_ENABLE,
+    MSG_INTR_DISABLE,
+    MSG_INTR_STATUS_GET,
+    MSG_NOTIFICATION_REGISTER_FOR,
+    MSG_NOTIFICATION_CANCEL,
+    MSG_NOTIFICATION_WAIT,
+    MSG_NOTIFICATION_STATUS,
+    MSG_DMA_CHANNEL_OPEN,
+    MSG_DMA_GET_PROPERTIES,
+    MSG_DMA_SET_PROPERTIES,
+    MSG_DMA_CONTROL,
+    MSG_DMA_STATUS,
+    MSG_DMA_TRANSFER_BLOCK,
+    MSG_DMA_TRANSFER_USER_BUFFER,
+    MSG_DMA_CHANNEL_CLOSE,
+    MSG_PERFORMANCE_INIT_PROPERTIES,
+    MSG_PERFORMANCE_MONITOR_CTRL,
+    MSG_PERFORMANCE_RESET_COUNTERS,
+    MSG_PERFORMANCE_GET_COUNTERS,
+    MSG_MH_GET_PROPERTIES,
+    MSG_MH_MIGRATE_DS_PORTS,
+    MSG_NT_PROBE_REQ_ID,
+    MSG_NT_LUT_PROPERTIES,
+    MSG_NT_LUT_ADD,
+    MSG_NT_LUT_DISABLE
+} DRIVER_MSGS;
+
+
+
+
+#define PLX_IOCTL_DRIVER_VERSION                IOCTL_MSG( MSG_DRIVER_VERSION )
+#define PLX_IOCTL_DRIVER_PROPERTIES             IOCTL_MSG( MSG_DRIVER_PROPERTIES )
+#define PLX_IOCTL_DRIVER_SCHEDULE_RESCAN        IOCTL_MSG( MSG_DRIVER_SCHEDULE_RESCAN )
+#define PLX_IOCTL_CHIP_TYPE_GET                 IOCTL_MSG( MSG_CHIP_TYPE_GET )
+#define PLX_IOCTL_CHIP_TYPE_SET                 IOCTL_MSG( MSG_CHIP_TYPE_SET )
+#define PLX_IOCTL_GET_PORT_PROPERTIES           IOCTL_MSG( MSG_GET_PORT_PROPERTIES )
+
+#define PLX_IOCTL_PCI_DEVICE_FIND               IOCTL_MSG( MSG_PCI_DEVICE_FIND )
+#define PLX_IOCTL_PCI_DEVICE_RESET              IOCTL_MSG( MSG_PCI_DEVICE_RESET )
+#define PLX_IOCTL_PCI_BAR_PROPERTIES            IOCTL_MSG( MSG_PCI_BAR_PROPERTIES )
+#define PLX_IOCTL_PCI_BAR_MAP                   IOCTL_MSG( MSG_PCI_BAR_MAP )
+#define PLX_IOCTL_PCI_BAR_UNMAP                 IOCTL_MSG( MSG_PCI_BAR_UNMAP )
+
+#define PLX_IOCTL_PCI_REGISTER_READ             IOCTL_MSG( MSG_PCI_REGISTER_READ )
+#define PLX_IOCTL_PCI_REGISTER_WRITE            IOCTL_MSG( MSG_PCI_REGISTER_WRITE )
+#define PLX_IOCTL_PCI_REG_READ_BYPASS_OS        IOCTL_MSG( MSG_PCI_REG_READ_BYPASS_OS )
+#define PLX_IOCTL_PCI_REG_WRITE_BYPASS_OS       IOCTL_MSG( MSG_PCI_REG_WRITE_BYPASS_OS )
+
+#define PLX_IOCTL_REGISTER_READ                 IOCTL_MSG( MSG_REGISTER_READ )
+#define PLX_IOCTL_REGISTER_WRITE                IOCTL_MSG( MSG_REGISTER_WRITE )
+#define PLX_IOCTL_MAPPED_REGISTER_READ          IOCTL_MSG( MSG_MAPPED_REGISTER_READ )
+#define PLX_IOCTL_MAPPED_REGISTER_WRITE         IOCTL_MSG( MSG_MAPPED_REGISTER_WRITE )
+#define PLX_IOCTL_MAILBOX_READ                  IOCTL_MSG( MSG_MAILBOX_READ )
+#define PLX_IOCTL_MAILBOX_WRITE                 IOCTL_MSG( MSG_MAILBOX_WRITE )
+
+#define PLX_IOCTL_PHYSICAL_MEM_ALLOCATE         IOCTL_MSG( MSG_PHYSICAL_MEM_ALLOCATE )
+#define PLX_IOCTL_PHYSICAL_MEM_FREE             IOCTL_MSG( MSG_PHYSICAL_MEM_FREE )
+#define PLX_IOCTL_PHYSICAL_MEM_MAP              IOCTL_MSG( MSG_PHYSICAL_MEM_MAP )
+#define PLX_IOCTL_PHYSICAL_MEM_UNMAP            IOCTL_MSG( MSG_PHYSICAL_MEM_UNMAP )
+#define PLX_IOCTL_COMMON_BUFFER_PROPERTIES      IOCTL_MSG( MSG_COMMON_BUFFER_PROPERTIES )
+
+#define PLX_IOCTL_IO_PORT_READ                  IOCTL_MSG( MSG_IO_PORT_READ )
+#define PLX_IOCTL_IO_PORT_WRITE                 IOCTL_MSG( MSG_IO_PORT_WRITE )
+#define PLX_IOCTL_PCI_BAR_SPACE_READ            IOCTL_MSG( MSG_PCI_BAR_SPACE_READ )
+#define PLX_IOCTL_PCI_BAR_SPACE_WRITE           IOCTL_MSG( MSG_PCI_BAR_SPACE_WRITE )
+
+#define PLX_IOCTL_VPD_READ                      IOCTL_MSG( MSG_VPD_READ )
+#define PLX_IOCTL_VPD_WRITE                     IOCTL_MSG( MSG_VPD_WRITE )
+
+#define PLX_IOCTL_EEPROM_PRESENT                IOCTL_MSG( MSG_EEPROM_PRESENT )
+#define PLX_IOCTL_EEPROM_PROBE                  IOCTL_MSG( MSG_EEPROM_PROBE )
+#define PLX_IOCTL_EEPROM_GET_ADDRESS_WIDTH      IOCTL_MSG( MSG_EEPROM_GET_ADDRESS_WIDTH )
+#define PLX_IOCTL_EEPROM_SET_ADDRESS_WIDTH      IOCTL_MSG( MSG_EEPROM_SET_ADDRESS_WIDTH )
+#define PLX_IOCTL_EEPROM_CRC_GET                IOCTL_MSG( MSG_EEPROM_CRC_GET )
+#define PLX_IOCTL_EEPROM_CRC_UPDATE             IOCTL_MSG( MSG_EEPROM_CRC_UPDATE )
+#define PLX_IOCTL_EEPROM_READ_BY_OFFSET         IOCTL_MSG( MSG_EEPROM_READ_BY_OFFSET )
+#define PLX_IOCTL_EEPROM_WRITE_BY_OFFSET        IOCTL_MSG( MSG_EEPROM_WRITE_BY_OFFSET )
+#define PLX_IOCTL_EEPROM_READ_BY_OFFSET_16      IOCTL_MSG( MSG_EEPROM_READ_BY_OFFSET_16 )
+#define PLX_IOCTL_EEPROM_WRITE_BY_OFFSET_16     IOCTL_MSG( MSG_EEPROM_WRITE_BY_OFFSET_16 )
+
+#define PLX_IOCTL_INTR_ENABLE                   IOCTL_MSG( MSG_INTR_ENABLE )
+#define PLX_IOCTL_INTR_DISABLE                  IOCTL_MSG( MSG_INTR_DISABLE )
+#define PLX_IOCTL_INTR_STATUS_GET               IOCTL_MSG( MSG_INTR_STATUS_GET )
+#define PLX_IOCTL_NOTIFICATION_REGISTER_FOR     IOCTL_MSG( MSG_NOTIFICATION_REGISTER_FOR )
+#define PLX_IOCTL_NOTIFICATION_CANCEL           IOCTL_MSG( MSG_NOTIFICATION_CANCEL )
+#define PLX_IOCTL_NOTIFICATION_WAIT             IOCTL_MSG( MSG_NOTIFICATION_WAIT )
+#define PLX_IOCTL_NOTIFICATION_STATUS           IOCTL_MSG( MSG_NOTIFICATION_STATUS )
+
+#define PLX_IOCTL_DMA_CHANNEL_OPEN              IOCTL_MSG( MSG_DMA_CHANNEL_OPEN )
+#define PLX_IOCTL_DMA_GET_PROPERTIES            IOCTL_MSG( MSG_DMA_GET_PROPERTIES )
+#define PLX_IOCTL_DMA_SET_PROPERTIES            IOCTL_MSG( MSG_DMA_SET_PROPERTIES )
+#define PLX_IOCTL_DMA_CONTROL                   IOCTL_MSG( MSG_DMA_CONTROL )
+#define PLX_IOCTL_DMA_STATUS                    IOCTL_MSG( MSG_DMA_STATUS )
+#define PLX_IOCTL_DMA_TRANSFER_BLOCK            IOCTL_MSG( MSG_DMA_TRANSFER_BLOCK )
+#define PLX_IOCTL_DMA_TRANSFER_USER_BUFFER      IOCTL_MSG( MSG_DMA_TRANSFER_USER_BUFFER )
+#define PLX_IOCTL_DMA_CHANNEL_CLOSE             IOCTL_MSG( MSG_DMA_CHANNEL_CLOSE )
+
+#define PLX_IOCTL_PERFORMANCE_INIT_PROPERTIES   IOCTL_MSG( MSG_PERFORMANCE_INIT_PROPERTIES )
+#define PLX_IOCTL_PERFORMANCE_MONITOR_CTRL      IOCTL_MSG( MSG_PERFORMANCE_MONITOR_CTRL )
+#define PLX_IOCTL_PERFORMANCE_RESET_COUNTERS    IOCTL_MSG( MSG_PERFORMANCE_RESET_COUNTERS )
+#define PLX_IOCTL_PERFORMANCE_GET_COUNTERS      IOCTL_MSG( MSG_PERFORMANCE_GET_COUNTERS )
+
+#define PLX_IOCTL_MH_GET_PROPERTIES             IOCTL_MSG( MSG_MH_GET_PROPERTIES )
+#define PLX_IOCTL_MH_MIGRATE_DS_PORTS           IOCTL_MSG( MSG_MH_MIGRATE_DS_PORTS )
+
+#define PLX_IOCTL_NT_PROBE_REQ_ID               IOCTL_MSG( MSG_NT_PROBE_REQ_ID )
+#define PLX_IOCTL_NT_LUT_PROPERTIES             IOCTL_MSG( MSG_NT_LUT_PROPERTIES )
+#define PLX_IOCTL_NT_LUT_ADD                    IOCTL_MSG( MSG_NT_LUT_ADD )
+#define PLX_IOCTL_NT_LUT_DISABLE                IOCTL_MSG( MSG_NT_LUT_DISABLE )
+
+
+// Restore previous pack value
+#pragma pack( pop )
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/PlxLists.h b/Plxlibrary/PlxLists.h
new file mode 100755
index 0000000..2d9733d
--- /dev/null
+++ b/Plxlibrary/PlxLists.h
@@ -0,0 +1,154 @@
+#ifndef __PLX_LISTS_H
+#define __PLX_LISTS_H
+
+/*******************************************************************************
+ * Copyright 2013-2015 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      PlxLists.h
+ *
+ * Description:
+ *
+ *      Generic double-linked list support
+ *
+ * Revision History:
+ *
+ *      02-01-10 : PLX SDK v6.40
+ *
+ ******************************************************************************/
+
+
+#include "PlxTypes.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+/**********************************************
+ *               Definitions
+ *********************************************/
+
+// Define list functions
+// Declare and initialize a list
+#define PLX_LIST_HEAD_INIT(name)                            { &(name), &(name) }
+#define PLX_LIST_HEAD(name)                                 struct _PLX_LIST_ENTRY = PLX_LIST_HEAD_INIT(name)
+
+// Calculate the address of the base of the structure given its type, and an
+// address of a field within the structure.
+#define PLX_CONTAINING_RECORD(address, type, field)         ((type *)( \
+                                                             (char*)(address) - \
+                                                             (PLX_UINT_PTR)(&((type *)0)->field)))
+
+// Locked list operations
+#define Plx_ExInterlockedInsertTailList(List,Entry,Lock)    Plx_InsertTailList( (List), (Entry) )
+#define Plx_ExInterlockedInsertHeadList(List,Entry,Lock)    Plx_InsertHeadList( (List), (Entry) )
+
+
+//  Doubly linked list structure
+typedef struct _PLX_LIST_ENTRY
+{
+    struct _PLX_LIST_ENTRY *Flink;
+    struct _PLX_LIST_ENTRY *Blink;
+} PLX_LIST_ENTRY;
+
+
+#if defined(PLX_DOS)
+    #define CONTAINING_RECORD                   PLX_CONTAINING_RECORD
+    #define ExInterlockedInsertTailList         Plx_ExInterlockedInsertTailList
+    #define ExInterlockedInsertHeadList         Plx_ExInterlockedInsertHeadList
+    #define InitializeListHead                  Plx_InitializeListHead
+    #define IsListEmpty                         Plx_IsListEmpty
+    #define RemoveHeadList                      Plx_RemoveHeadList
+    #define RemoveEntryList                     Plx_RemoveEntryList
+    #define InsertTailList                      Plx_InsertTailList
+    #define InsertHeadList                      Plx_InsertHeadList
+    typedef PLX_LIST_ENTRY                      LIST_ENTRY;
+#endif
+
+
+
+
+/**********************************************
+ *               Functions
+ *********************************************/
+VOID
+Plx_InitializeListHead(
+    PLX_LIST_ENTRY *ListHead
+    );
+
+BOOLEAN
+Plx_IsListEmpty(
+    const PLX_LIST_ENTRY * ListHead
+    );
+
+BOOLEAN
+Plx_RemoveEntryList(
+    PLX_LIST_ENTRY *Entry
+    );
+
+PLX_LIST_ENTRY*
+Plx_RemoveHeadList(
+    PLX_LIST_ENTRY *ListHead
+    );
+
+PLX_LIST_ENTRY*
+Plx_RemoveTailList(
+    PLX_LIST_ENTRY *ListHead
+    );
+
+VOID
+Plx_InsertTailList(
+    PLX_LIST_ENTRY *ListHead,
+    PLX_LIST_ENTRY *Entry
+    );
+
+VOID
+Plx_InsertHeadList(
+    PLX_LIST_ENTRY *ListHead,
+    PLX_LIST_ENTRY *Entry
+    );
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/PlxPci_9054_Func.h b/Plxlibrary/PlxPci_9054_Func.h
new file mode 100755
index 0000000..7d83a65
--- /dev/null
+++ b/Plxlibrary/PlxPci_9054_Func.h
@@ -0,0 +1,99 @@
+#ifndef     __PLXPCI_9054_FUNC_H
+#define     __PLXPCI_9054_FUNC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef PLX_LINUX
+#define PLX_LINUX
+#endif
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      PlxPci_9054_Func.h
+ *
+ * Description:
+ *
+ *      
+ *
+ ******************************************************************************/
+
+#include "PlxTypes.h"
+#include "PlxApi.h"
+#include "PlxInit.h"
+
+
+
+typedef enum __REGISTER_SET{
+    Pci9054,
+    Lcr9054,
+    Dma9054,
+    Eep9054
+}REGISTER_SET;
+/**********************************************
+ *               Functions
+ *********************************************/
+BOOLEAN PlxPci_9054_SelDevice(U32 Dkey);
+
+BOOLEAN PlxPci_9054_Open(void);
+
+
+BOOLEAN
+PlxPci_9054_DMATransfer(
+			U32      			LocalAddress,
+            VOID      			*pUserBuffer,
+            U32		 			BufferByteCount
+			);
+
+BOOLEAN 
+PlxPci_9054_ReadBar(
+			U32		PBOffset,						 
+			VOID	*pUserBuffer,
+            U32     UserBuffersize
+			);
+
+BOOLEAN 
+PlxPci_9054_WriteBar(
+			U32		PBOffset,						 
+			VOID	*pUserBuffer,
+            U32     UserBuffersize
+			);
+
+BOOLEAN 
+PlxPci_9054_ReadEep(
+            U16		RegOffset,
+            U32		*RegBuffer
+			);
+
+BOOLEAN 
+PlxPci_9054_WriteEep(
+			U16					RegOffset,
+			U32					RegVal 
+			);
+
+BOOLEAN PlxPci_9054_Reset(void);
+
+BOOLEAN PlxPci_9054_Close(void);
+
+BOOLEAN PlxPci_9054_LoadE2pToFPGA(void);
+
+BOOLEAN PlxPci_9054_EnableInterrupt(void);
+
+BOOLEAN PlxPci_9054_DisableInterrupt(void);
+
+BOOLEAN PlxPci_9054_WaitForInterrupt(U32 TimeOut);
+
+BOOLEAN PlxPci_9054_ChipTypeGet(U8      Revision,
+                                U16     ChipType);
+
+BOOLEAN PlxPci_9054_DMAChannelOpen(void);
+
+BOOLEAN PlxPci_9054_DMAChannelClose(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/PlxStat.h b/Plxlibrary/PlxStat.h
new file mode 100755
index 0000000..cc642bb
--- /dev/null
+++ b/Plxlibrary/PlxStat.h
@@ -0,0 +1,158 @@
+#ifndef __PLX_STATUS_H
+#define __PLX_STATUS_H
+
+/*******************************************************************************
+ * Copyright 2013-2015 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      PlxStat.h
+ *
+ * Description:
+ *
+ *      This file defines all the status codes for PLX SDK
+ *
+ * Revision:
+ *
+ *      08-01-14 : PLX SDK v7.20
+ *
+ ******************************************************************************/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+/******************************************
+ *             Definitions
+ *****************************************/
+#define PLX_STATUS_START               0x200   // Starting status code
+
+// Return type
+typedef int    PLX_STATUS;
+
+
+// API Return Code Values
+typedef enum _PLX_STATUS_CODE
+{
+    PLX_STATUS_OK               = PLX_STATUS_START,
+    PLX_STATUS_FAILED,
+    PLX_STATUS_NULL_PARAM,
+    PLX_STATUS_UNSUPPORTED,
+    PLX_STATUS_NO_DRIVER,
+    PLX_STATUS_INVALID_OBJECT,
+    PLX_STATUS_VER_MISMATCH,
+    PLX_STATUS_INVALID_OFFSET,
+    PLX_STATUS_INVALID_DATA,
+    PLX_STATUS_INVALID_SIZE,
+    PLX_STATUS_INVALID_ADDR,
+    PLX_STATUS_INVALID_ACCESS,
+    PLX_STATUS_INSUFFICIENT_RES,
+    PLX_STATUS_TIMEOUT,
+    PLX_STATUS_CANCELED,
+    PLX_STATUS_COMPLETE,
+    PLX_STATUS_PAUSED,
+    PLX_STATUS_IN_PROGRESS,
+    PLX_STATUS_PAGE_GET_ERROR,
+    PLX_STATUS_PAGE_LOCK_ERROR,
+    PLX_STATUS_LOW_POWER,
+    PLX_STATUS_IN_USE,
+    PLX_STATUS_DISABLED,
+    PLX_STATUS_PENDING,
+    PLX_STATUS_NOT_FOUND,
+    PLX_STATUS_INVALID_STATE,
+    PLX_STATUS_BUFF_TOO_SMALL,
+    PLX_STATUS_RSVD_LAST_ERROR    // Do not add API errors below this line
+} PLX_STATUS_CODE;
+
+
+
+// Definitions to support existing applications. Will be removed in future.
+#if 1
+#define ApiSuccess                      PLX_STATUS_OK
+#define ApiFailed                       PLX_STATUS_FAILED
+#define ApiNullParam                    PLX_STATUS_NULL_PARAM
+#define ApiUnsupportedFunction          PLX_STATUS_UNSUPPORTED
+#define ApiNoActiveDriver               PLX_STATUS_NO_DRIVER
+#define ApiConfigAccessFailed           PLX_STATUS_FAILED
+#define ApiInvalidDeviceInfo            PLX_STATUS_INVALID_OBJECT
+#define ApiInvalidDriverVersion         PLX_STATUS_VER_MISMATCH
+#define ApiInvalidPciSpace              PLX_STATUS_INVALID_ADDR
+#define ApiInvalidOffset                PLX_STATUS_INVALID_OFFSET
+#define ApiInvalidData                  PLX_STATUS_INVALID_DATA
+#define ApiInvalidSize                  PLX_STATUS_INVALID_SIZE
+#define ApiInvalidAddress               PLX_STATUS_INVALID_ADDR
+#define ApiInvalidAccessType            PLX_STATUS_INVALID_ACCESS
+#define ApiInvalidIndex                 PLX_STATUS_INVALID_DATA
+#define ApiInvalidHandle                PLX_STATUS_INVALID_ACCESS
+#define ApiInvalidPowerState            PLX_STATUS_INVALID_STATE
+#define ApiInvalidIopSpace              PLX_STATUS_INVALID_ACCESS
+#define ApiInvalidBusIndex              PLX_STATUS_INVALID_DATA
+#define ApiInsufficientResources        PLX_STATUS_INSUFFICIENT_RES
+#define ApiWaitTimeout                  PLX_STATUS_TIMEOUT
+#define ApiWaitCanceled                 PLX_STATUS_CANCELED
+#define ApiDmaDone                      PLX_STATUS_COMPLETE
+#define ApiDmaPaused                    PLX_STATUS_PAUSED
+#define ApiDmaChannelInvalid            PLX_STATUS_INVALID_ADDR
+#define ApiDmaInProgress                PLX_STATUS_IN_PROGRESS
+#define ApiDmaSglPagesGetError          PLX_STATUS_PAGE_GET_ERROR
+#define ApiDmaSglPagesLockError         PLX_STATUS_PAGE_LOCK_ERROR
+#define ApiDmaChannelUnavailable        PLX_STATUS_INVALID_ACCESS
+#define ApiDmaCommandInvalid            PLX_STATUS_INVALID_DATA
+#define ApiDmaInvalidChannelPriority    PLX_STATUS_INVALID_DATA
+#define ApiPowerDown                    PLX_STATUS_LOW_POWER
+#define ApiDeviceInUse                  PLX_STATUS_IN_USE
+#define ApiDeviceDisabled               PLX_STATUS_DISABLED
+#define ApiPending                      PLX_STATUS_PENDING
+#define ApiObjectNotFound               PLX_STATUS_NOT_FOUND
+#define ApiInvalidState                 PLX_STATUS_INVALID_STATE
+#define ApiBufferTooSmall               PLX_STATUS_BUFF_TOO_SMALL
+#define ApiMuFifoEmpty                  PLX_STATUS_NOT_FOUND
+#define ApiMuFifoFull                   PLX_STATUS_INSUFFICIENT_RES
+#define ApiHSNotSupported               PLX_STATUS_UNSUPPORTED
+#define ApiVPDNotSupported              PLX_STATUS_UNSUPPORTED
+#define ApiLastError                    PLX_STATUS_RSVD_LAST_ERROR
+#endif
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/PlxTypes.h b/Plxlibrary/PlxTypes.h
new file mode 100755
index 0000000..2194af1
--- /dev/null
+++ b/Plxlibrary/PlxTypes.h
@@ -0,0 +1,1062 @@
+#ifndef __PLX_TYPES_H
+#define __PLX_TYPES_H
+
+/*******************************************************************************
+ * Copyright 2019-2020 Broadcom Inc.
+ * Copyright 2013-2018 Avago Technologies
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      PlxTypes.h
+ *
+ * Description:
+ *
+ *      This file includes SDK types and definitions
+ *
+ * Revision:
+ *
+ *      01-01-20 : PCI/PCIe SDK v8.10
+ *
+ ******************************************************************************/
+
+
+#include "Plx.h"
+#include "PlxDefCk.h"
+#include "PlxStat.h"
+#include "PciTypes.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+// Set structure packing for consistentcy in kernel/user levels & save current
+#pragma pack( push, 4 )
+
+
+
+
+/******************************************
+ *   Definitions for Code Portability
+ ******************************************/
+// Memory set and copy
+#if !defined(PLX_MSWINDOWS)
+    #define RtlZeroMemory(pDest, count)         memset((pDest), 0, (count))
+    #define RtlCopyMemory(pDest, pSrc, count)   memcpy((pDest), (pSrc), (count))
+    #define RtlFillMemory(pDest, count, value)  memset((pDest), (value), (count))
+#endif
+
+// Count number of bits of supplied data type
+#define PLX_BYTE_TO_BIT_COUNT( bytes )          ((bytes) * 8)
+
+// Convert pointer to an integer
+#define PLX_PTR_TO_INT( ptr )                   ((PLX_UINT_PTR)(ptr))
+
+// Convert integer to a pointer
+#define PLX_INT_TO_PTR( intval )                ((VOID*)(PLX_UINT_PTR)(intval))
+
+// Macros that guarantee correct endian format regardless of CPU platform
+#if defined(PLX_BIG_ENDIAN)
+    #define PLX_LE_DATA_32(value)               EndianSwap32( (value) )
+    #define PLX_BE_DATA_32(value)               (value)
+#else
+    #define PLX_LE_DATA_32(value)               (value)
+    #define PLX_BE_DATA_32(value)               EndianSwap32( (value) )
+#endif
+
+// Macros to support portable type casting on BE/LE platforms
+#if defined(PLX_BIG_ENDIAN)
+    #define PLX_64_HIGH_32(value)               ((U32)((U64)value))
+    #define PLX_64_LOW_32(value)                ((U32)(((U64)value) >> 32))
+
+    #define PLX_CAST_64_TO_8_PTR( ptr64 )       (U8*) ((U8*)PLX_INT_TO_PTR(ptr64) + (7 * sizeof(U8)))
+    #define PLX_CAST_64_TO_16_PTR( ptr64 )      (U16*)((U8*)PLX_INT_TO_PTR(ptr64) + (6 * sizeof(U8)))
+    #define PLX_CAST_64_TO_32_PTR( ptr64 )      (U32*)((U8*)PLX_INT_TO_PTR(ptr64) + sizeof(U32))
+
+    #define PLX_LE_U32_BIT( pos )               ((U32)(1 << (31 - (pos))))
+#else
+    #define PLX_64_HIGH_32( value )             ((U32)(((U64)value) >> 32))
+    #define PLX_64_LOW_32( value )              ((U32)((U64)value))
+
+    #define PLX_CAST_64_TO_8_PTR( ptr64 )       (U8*) PLX_INT_TO_PTR(ptr64)
+    #define PLX_CAST_64_TO_16_PTR( ptr64 )      (U16*)PLX_INT_TO_PTR(ptr64)
+    #define PLX_CAST_64_TO_32_PTR( ptr64 )      (U32*)PLX_INT_TO_PTR(ptr64)
+
+    #define PLX_LE_U32_BIT( pos )               ((U32)(1 << (pos)))
+#endif
+
+
+
+/******************************************
+ *      Miscellaneous definitions
+ ******************************************/
+#if !defined(VOID)
+    typedef void              VOID;
+#endif
+
+// Linux actypes.h contains conflicting definition for BOOLEAN
+#if (!defined(PLX_MSWINDOWS)) || defined(PLX_VXD_DRIVER)
+    #if !defined(BOOLEAN) && !defined(__ACTYPES_H__)
+        typedef S8            BOOLEAN;
+    #endif
+#endif
+
+#if !defined(PLX_MSWINDOWS)
+    #if !defined(BOOL)
+        typedef S8            BOOL;
+    #endif
+#endif
+
+#if !defined(NULL)
+    #define NULL              ((VOID *) 0x0)
+#endif
+
+#if !defined(TRUE)
+    #define TRUE              1
+#endif
+
+#if !defined(FALSE)
+    #define FALSE             0
+#endif
+
+// Min/Max
+#define PEX_MIN(v1,v2)        ( (v1) < (v2) ? (v1) : (v2) )
+#define PEX_MAX(v1,v2)        ( (v1) > (v2) ? (v1) : (v2) )
+
+// Round up/down based on power of 2
+#define PEX_P2_ROUND_UP( val, align )       ( ((val) + ((align) - 1)) & ~(align - 1) )
+#define PEX_P2_ROUND_DOWN( val, align )     ( (val) & ~((align) - 1) )
+
+// Calculate time difference between 2 timeb structures
+#define PLX_DIFF_TIMEB(time1,time0)         ( ((double)((time1).time - (time0).time)) + \
+                                              (((double)(time1).millitm - (time0).millitm) / 1000) )
+
+#if defined(PLX_MSWINDOWS)
+    #define PLX_TIMEOUT_INFINITE        INFINITE
+    #define PLX_MEM_POOL_TAG            '_XLP'  // "PLX_" tag for driver mem alloc
+#elif defined(PLX_LINUX) || defined(PLX_LINUX_DRIVER)
+    #define PLX_TIMEOUT_INFINITE        MAX_SCHEDULE_TIMEOUT
+
+    /*********************************************************
+     * Convert milliseconds to jiffies.  The following
+     * formula is used:
+     *
+     *                      ms * HZ
+     *           jiffies = ---------
+     *                       1,000
+     *
+     *  where:  HZ      = System-defined clock ticks per second
+     *          ms      = Timeout in milliseconds
+     *          jiffies = Number of HZ's per second
+     ********************************************************/
+    #define Plx_ms_to_jiffies( ms )     ( ((ms) * HZ) / 1000 )
+    #define Plx_jiffies_to_ms( jiff )   ( ((jiff) * 1000) / HZ )
+#endif
+
+
+
+/******************************************
+ *   Definitions for Generic Bitmasks
+ ******************************************/
+/// Declare a generic bitmask variable with arbitrary size (auto-aligns to 32-bit multiple)
+#define PEX_BITMASK_T(Name,Bits)            U32 (Name)[ ((Bits) + 31) / 32 ]
+
+// Set a bit in generic bitmask variable
+#define PEX_BITMASK_SET(Mask,Bit)           ( (Mask)[ (Bit) / 32 ] |= ((U32)1 << ((Bit) % 32)) )
+
+// Set all bits in generic bitmask variable
+#define PEX_BITMASK_SET_ALL(Mask)           memset( (Mask), 0xFF, sizeof((Mask)) )
+
+// Clear a bit in generic bitmask variable
+#define PEX_BITMASK_CLEAR(Mask,Bit)         ( (Mask)[ (Bit) / 32 ] &= ~((U32)1 << ((Bit) % 32)) )
+
+// Clear all bits in generic bitmask variable
+#define PEX_BITMASK_CLEAR_ALL(Mask)         memset( (Mask), 0, sizeof((Mask)) )
+
+// Returns 32-bit DW port mask at provided DW index
+#define PEX_BITMASK_GET_DW(Mask,Idx)        ((Mask)[Idx])
+
+// Sets 32-bit DW port mask at provided DW index
+#define PEX_BITMASK_SET_DW(Mask,Idx,Val)    ((Mask)[Idx] = (Val))
+
+// Copies one mask to another
+#define PEX_BITMASK_COPY(Src,Dest)          memcpy( (Dest), (Src), sizeof((Dest)) )
+
+// Test whether a specific bit is set in generic bitmask variable
+#define PEX_BITMASK_TEST(Mask,Bit)          ( ((Mask)[ (Bit) / 32 ] & ((U32)1 << ((Bit) % 32))) != 0 )
+
+// Test whether any bit is set in generic bitmask variable
+#define PEX_BITMASK_TEST_ANY(Mask)          __PEX_BITMASK_TEST_ANY( (Mask), sizeof( (Mask) ) )
+
+// Helper function for PEX_BITMASK_TEST_ANY macro
+static __inline U8 __PEX_BITMASK_TEST_ANY( U32 *PtrBitMask, U32 ByteSize )
+{
+    U32 idx = 0;
+
+    while ( idx < (ByteSize / sizeof(U32)) )
+    {
+        if (PtrBitMask[ idx ] != 0)
+        {
+            return TRUE;
+        }
+        idx++;
+    }
+    return FALSE;
+}
+
+// Return the count of set bits in a mask
+#define PEX_BITMASK_GET_SET_COUNT(Mask)     __PEX_BITMASK_GET_SET_COUNT( (Mask), sizeof( (Mask) ) )
+
+// Helper function for PEX_BITMASK_GET_SET_COUNT macro
+static __inline U32 __PEX_BITMASK_GET_SET_COUNT( U32 *PtrBitMask, U32 ByteSize )
+{
+    U32 bit = 0;
+    U32 bitCount = 0;
+
+    while (bit < (ByteSize * 8))
+    {
+        bitCount += PEX_BITMASK_TEST( PtrBitMask, bit );
+        bit++;
+    }
+    return bitCount;
+}
+
+
+
+/******************************************
+ *   PLX-specific types & structures
+ ******************************************/
+// Mode PLX API uses to access device
+typedef enum _PLX_API_MODE
+{
+    PLX_API_MODE_PCI,                   // Device accessed via PLX driver over PCI/PCIe
+    PLX_API_MODE_I2C_AARDVARK,          // Device accessed via Aardvark I2C USB
+    PLX_API_MODE_MDIO_SPLICE,           // Device accessed via Splice MDIO USB
+    PLX_API_MODE_SDB,                   // Device accessed via Serial Debug Port
+    PLX_API_MODE_TCP                    // Device accessed via TCP/IP
+} PLX_API_MODE;
+
+
+// Supported UART cable connections for SDB
+typedef enum _SDB_UART_CABLE
+{
+    SDB_UART_CABLE_DEFAULT     = 0,     // Default connection
+    SDB_UART_CABLE_UART        = 1,     // Standard COMx connection
+    SDB_UART_CABLE_USB         = 2      // USB-to-serial cable
+} SDB_UART_CABLE;
+
+
+// Baud rates supported by SDB
+typedef enum _SDB_BAUD_RATE
+{
+    SDB_BAUD_RATE_DEFAULT      = 0,     // Default rate
+    SDB_BAUD_RATE_19200        = 1,     // 19,200 BAUD
+    SDB_BAUD_RATE_115200       = 2      // 115,200 BAUD
+} SDB_BAUD_RATE;
+
+
+// Access Size Type
+typedef enum _PLX_ACCESS_TYPE
+{
+    BitSize8,
+    BitSize16,
+    BitSize32,
+    BitSize64
+} PLX_ACCESS_TYPE;
+
+
+// PLX chip families
+typedef enum _PLX_CHIP_FAMILY
+{
+    PLX_FAMILY_NONE = 0,
+    PLX_FAMILY_UNKNOWN,
+    PLX_FAMILY_BRIDGE_P2L,              // 9000 series & 8311
+    PLX_FAMILY_BRIDGE_PCI_P2P,          // 6000 series
+    PLX_FAMILY_BRIDGE_PCIE_P2P,         // 8111,8112,8114
+    PLX_FAMILY_ALTAIR,                  // 8525,8533,8547,8548
+    PLX_FAMILY_ALTAIR_XL,               // 8505,8509
+    PLX_FAMILY_VEGA,                    // 8516,8524,8532
+    PLX_FAMILY_VEGA_LITE,               // 8508,8512,8517,8518
+    PLX_FAMILY_DENEB,                   // 8612,8616,8624,8632,8647,8648
+    PLX_FAMILY_SIRIUS,                  // 8604,8606,8608,8609,8613,8614,8615
+                                        //   8617,8618,8619
+    PLX_FAMILY_CYGNUS,                  // 8625,8636,8649,8664,8680,8696
+    PLX_FAMILY_SCOUT,                   // 8700
+    PLX_FAMILY_DRACO_1,                 // 8712,8716,8724,8732,8747,8748,8749
+    PLX_FAMILY_DRACO_2,                 // 8713,8717,8725,8733 + [Draco 1 rev BA]
+    PLX_FAMILY_MIRA,                    // 2380,3380,3382,8603,8605
+    PLX_FAMILY_CAPELLA_1,               // 8714,8718,8734,8750,8764,8780,8796
+    PLX_FAMILY_CAPELLA_2,               // 9712,9716,9733,9749,9750,9765,9781,9797
+    PLX_FAMILY_ATLAS,                   // C010,C011,C012
+    PLX_FAMILY_LAST_ENTRY               // -- Must be final entry --
+} PLX_CHIP_FAMILY;
+
+
+// PLX chip configured mode
+typedef enum _PLX_CHIP_MODE
+{
+    PLX_CHIP_MODE_UNKNOWN,
+    PLX_CHIP_MODE_STANDARD,             // Standard switch fan-out mode
+    PLX_CHIP_MODE_STD_LEGACY_NT,        // Standard mode with NT but no parent DS P2P
+    PLX_CHIP_MODE_STD_NT_DS_P2P,        // Standard mode with NT & parent DS P2P
+    PLX_CHIP_MODE_VIRT_SW,              // Virtual Switch (VS) mode
+    PLX_CHIP_MODE_FABRIC,               // PCIe fabric mode
+    PLX_CHIP_MODE_ROOT_COMPLEX,         // RC mode
+    PLX_CHIP_MODE_LEGACY_ADAPTER        // MIRA legacy adapter mode
+} PLX_CHIP_MODE;
+
+
+// PLX port flags for mask
+typedef enum _PLX_FLAG_PORT
+{
+    // Flags for special port/device types
+    PLX_FLAG_PORT_NT_LINK_0     = 178,  // Bit for NT Link port 0
+    PLX_FLAG_PORT_NT_LINK_1     = 179,  // Bit for NT Link port 1
+    PLX_FLAG_PORT_NT_VIRTUAL_0  = 180,  // Bit for NT Virtual port 0
+    PLX_FLAG_PORT_NT_VIRTUAL_1  = 181,  // Bit for NT Virtual port 1
+    PLX_FLAG_PORT_NT_DS_P2P     = 182,  // Bit for NT DS P2P port (Virtual)
+    PLX_FLAG_PORT_DMA_RAM       = 183,  // Bit for DMA RAM
+    PLX_FLAG_PORT_DMA_0         = 184,  // Bit for DMA channel 3
+    PLX_FLAG_PORT_DMA_1         = 185,  // Bit for DMA channel 2
+    PLX_FLAG_PORT_DMA_2         = 186,  // Bit for DMA channel 1
+    PLX_FLAG_PORT_DMA_3         = 187,  // Bit for DMA ch 0 or Func 1 (all 4 ch)
+    PLX_FLAG_PORT_PCIE_TO_USB   = 188,  // Bit for PCIe-to-USB P2P or Root Port
+    PLX_FLAG_PORT_USB           = 189,  // Bit for USB Host/Bridge
+    PLX_FLAG_PORT_ALUT_0        = 190,  // Bit for ALUT RAM arrays 0
+    PLX_FLAG_PORT_ALUT_1        = 191,  // Bit for ALUT RAM arrays 1
+    PLX_FLAG_PORT_ALUT_2        = 192,  // Bit for ALUT RAM arrays 2
+    PLX_FLAG_PORT_ALUT_3        = 193,  // Bit for ALUT RAM arrays 3
+    PLX_FLAG_PORT_STN_REGS_S0   = 194,  // Bit for VS or Fabric mode station 0 specific regs
+    PLX_FLAG_PORT_STN_REGS_S1   = 195,  // Bit for VS or Fabric mode station 1 specific regs
+    PLX_FLAG_PORT_STN_REGS_S2   = 196,  // Bit for VS or Fabric mode station 2 specific regs
+    PLX_FLAG_PORT_STN_REGS_S3   = 197,  // Bit for VS or Fabric mode station 3 specific regs
+    PLX_FLAG_PORT_STN_REGS_S4   = 198,  // Bit for VS or Fabric mode station 4 specific regs
+    PLX_FLAG_PORT_STN_REGS_S5   = 199,  // Bit for VS or Fabric mode station 5 specific regs
+    PLX_FLAG_PORT_MAX           = 200,  // Bit for highest possible standard port
+
+	// Flags for internal fan out ports & endpoints
+    PLX_FLAG_PORT_INT_MGMT      = 253,  // Internal Management port (iSSW)
+    PLX_FLAG_PORT_INT_DS_0      = 224,  // Internal DS 0
+    PLX_FLAG_PORT_INT_DS_4      = 225,  // Internal DS 4
+    PLX_FLAG_PORT_INT_DS_8      = 226,  // Internal DS 8
+    PLX_FLAG_PORT_INT_DS_12     = 227,  // Internal DS 12
+    PLX_FLAG_PORT_INT_UP_0      = 232,  // Internal UP 0
+    PLX_FLAG_PORT_INT_UP_4      = 233,  // Internal UP 4
+    PLX_FLAG_PORT_INT_UP_8      = 234,  // Internal UP 8
+    PLX_FLAG_PORT_INT_UP_12     = 235,  // Internal UP 12
+    PLX_FLAG_PORT_GEP           = 251,  // GEP
+    PLX_FLAG_PORT_GEP_DS        = 255,  // GEP parent DS
+    PLX_FLAG_PORT_MPT0          = 247,  // MPT0
+    PLX_FLAG_PORT_MPT1          = 248,  // MPT1
+    PLX_FLAG_PORT_MPT2          = 249,  // MPT2
+    PLX_FLAG_PORT_MPT3          = 250   // MPT3
+} PLX_FLAG_PORT;
+
+
+// Generic states used internally by PLX software
+typedef enum _PLX_STATE
+{
+    PLX_STATE_OK,
+    PLX_STATE_NO_CHANGE,
+    PLX_STATE_WORKING,
+    PLX_STATE_ERROR,
+    PLX_STATE_ENABLED,
+    PLX_STATE_DISABLED,
+    PLX_STATE_UNINITIALIZED,
+    PLX_STATE_INITIALIZING,
+    PLX_STATE_INITIALIZED,
+    PLX_STATE_IDLE,
+    PLX_STATE_BUSY,
+    PLX_STATE_STARTED,
+    PLX_STATE_STARTING,
+    PLX_STATE_STOPPED,
+    PLX_STATE_STOPPING,
+    PLX_STATE_CANCELED,
+    PLX_STATE_DELETED,
+    PLX_STATE_MARKED_FOR_DELETE,
+    PLX_STATE_OK_TO_DELETE,
+    PLX_STATE_TRIGGERED,
+    PLX_STATE_PENDING,
+    PLX_STATE_WAITING,
+    PLX_STATE_TIMEOUT,
+    PLX_STATE_REQUESTING,
+    PLX_STATE_REQUESTED,
+    PLX_STATE_ACCEPTING,
+    PLX_STATE_ACCEPTED,
+    PLX_STATE_REJECTED,
+    PLX_STATE_COMPLETING,
+    PLX_STATE_COMPLETED,
+    PLX_STATE_CONNECTING,
+    PLX_STATE_CONNECTED,
+    PLX_STATE_DISCONNECTING,
+    PLX_STATE_DISCONNECTED
+} PLX_STATE;
+
+
+// BAR flags
+typedef enum _PLX_BAR_FLAG
+{
+    PLX_BAR_FLAG_MEM               = (1 << 0),
+    PLX_BAR_FLAG_IO                = (1 << 1),
+    PLX_BAR_FLAG_BELOW_1MB         = (1 << 2),
+    PLX_BAR_FLAG_32_BIT            = (1 << 3),
+    PLX_BAR_FLAG_64_BIT            = (1 << 4),
+    PLX_BAR_FLAG_PREFETCHABLE      = (1 << 5),
+    PLX_BAR_FLAG_UPPER_32          = (1 << 6),
+    PLX_BAR_FLAG_PROBED            = (1 << 7)
+} PLX_BAR_FLAG;
+
+
+// EEPROM status
+typedef enum _PLX_EEPROM_STATUS
+{
+    PLX_EEPROM_STATUS_NONE         = 0,     // Not present
+    PLX_EEPROM_STATUS_VALID        = 1,     // Present with valid data
+    PLX_EEPROM_STATUS_INVALID_DATA = 2,     // Present w/invalid data or CRC error
+    PLX_EEPROM_STATUS_BLANK        = PLX_EEPROM_STATUS_INVALID_DATA,
+    PLX_EEPROM_STATUS_CRC_ERROR    = PLX_EEPROM_STATUS_INVALID_DATA
+} PLX_EEPROM_STATUS;
+
+
+// EEPROM port numbers
+typedef enum _PLX_EEPROM_PORT
+{
+    PLX_EEPROM_PORT_NONE        = 0,
+    PLX_EEPROM_PORT_NT_VIRT_0   = 254,
+    PLX_EEPROM_PORT_NT_LINK_0   = 253,
+    PLX_EEPROM_PORT_NT_VIRT_1   = 252,
+    PLX_EEPROM_PORT_NT_LINK_1   = 251,
+    PLX_EEPROM_PORT_DMA_0       = 250,
+    PLX_EEPROM_PORT_DMA_1       = 249,
+    PLX_EEPROM_PORT_DMA_2       = 248,
+    PLX_EEPROM_PORT_DMA_3       = 247,
+    PLX_EEPROM_PORT_SHARED_MEM  = 246
+} PLX_EEPROM_PORT;
+
+
+// EEPROM CRC status
+typedef enum _PLX_CRC_STATUS
+{
+    PLX_CRC_INVALID             = 0,
+    PLX_CRC_VALID               = 1,
+    PLX_CRC_UNSUPPORTED         = 2,
+    PLX_CRC_UNKNOWN             = 3
+} PLX_CRC_STATUS;
+
+
+// SPI flags
+typedef enum _PEX_SPI_FLAGS
+{
+    PEX_SPI_FLAG_NONE           = 0,        // No flags
+    PEX_SPI_FLAG_USE_MM_RD      = (1 << 1), // Use mem-mapped read if supp
+    PEX_SPI_FLAG_DUAL_IO_SUPP   = (1 << 2), // Dual I/O supported
+    PEX_SPI_FLAG_QUAD_IO_SUPP   = (1 << 3)  // Dual I/O supported
+} PEX_SPI_FLAGS;
+
+
+// SPI I/O mode types
+typedef enum _PEX_SPI_IO_MODE
+{
+    PEX_SPI_IO_MODE_SERIAL      = 0,        // Standard serial mode
+    PEX_SPI_IO_MODE_DUAL_IO     = 1,        // Dual I/O mode
+    PEX_SPI_IO_MODE_QUAD_IO     = 2         // Quad I/O mode
+} PEX_SPI_IO_MODE;
+
+
+// Special value to indicate erase all of flash
+#define SPI_FLASH_ERASE_ALL     (U32)-1
+
+
+// PCI Express Link Speeds
+typedef enum _PLX_LINK_SPEED
+{
+    PLX_LINK_SPEED_2_5_GBPS     = 1,
+    PLX_LINK_SPEED_5_GBPS       = 2,
+    PLX_LINK_SPEED_8_GBPS       = 3,
+    PLX_LINK_SPEED_16_GBPS      = 4
+} PLX_LINK_SPEED;
+
+
+// Interrupt generation types
+typedef enum _PLX_IRQ_TYPE
+{
+    PLX_IRQ_TYPE_NONE           = 0,        // No interrupt
+    PLX_IRQ_TYPE_UNKNOWN        = 1,        // Undefined interrupt type
+    PLX_IRQ_TYPE_INTX           = 2,        // Legacy INTx interrupt (INTA,INTB,etc)
+    PLX_IRQ_TYPE_MSI            = 3,        // MSI interrupt
+    PLX_IRQ_TYPE_MSIX           = 4         // MSI-X interrupt
+} PLX_IRQ_TYPE;
+
+
+// Port types
+typedef enum _PLX_PORT_TYPE
+{
+    PLX_PORT_UNKNOWN            = 0xFF,
+    PLX_PORT_ENDPOINT           = 0,
+    PLX_PORT_LEGACY_ENDPOINT    = 1,
+    PLX_PORT_ROOT_PORT          = 4,
+    PLX_PORT_UPSTREAM           = 5,
+    PLX_PORT_DOWNSTREAM         = 6,
+    PLX_PORT_PCIE_TO_PCI_BRIDGE = 7,
+    PLX_PORT_PCI_TO_PCIE_BRIDGE = 8,
+    PLX_PORT_ROOT_ENDPOINT      = 9,
+    PLX_PORT_ROOT_EVENT_COLL    = 10
+} PLX_PORT_TYPE;
+
+
+// PLX-specific port types
+typedef enum _PLX_SPECIFIC_PORT_TYPE
+{
+    PLX_SPEC_PORT_UNKNOWN       = 0,            // Unknown port type
+    PLX_SPEC_PORT_INVALID       = 0xFF,         // Invalid port type
+    PLX_SPEC_PORT_NT_VIRTUAL    = 1,            // NT Virtual-side
+    PLX_SPEC_PORT_NT_LINK       = 2,            // NT Link-side
+    PLX_SPEC_PORT_UPSTREAM      = 3,            // Upstream port
+    PLX_SPEC_PORT_DOWNSTREAM    = 4,            // Downstream port
+    PLX_SPEC_PORT_P2P_BRIDGE    = 5,            // P2P bridge
+    PLX_SPEC_PORT_LEGACY_EP     = 6,            // Legacy EP
+    PLX_SPEC_PORT_DMA           = 7,            // DMA EP
+    PLX_SPEC_PORT_HOST          = 8,            // Host port
+    PLX_SPEC_PORT_FABRIC        = 9,            // Fabric port
+    PLX_SPEC_PORT_GEP           = 10,           // Global EP
+    PLX_SPEC_PORT_MPT           = 11,           // MPT SAS controller EP
+    PLX_SPEC_PORT_MPT_NO_SES    = 12,           // MPT EP (No SES)
+    PLX_SPEC_PORT_SYNTH_NIC     = 13,           // Synthetic NIC VF
+    PLX_SPEC_PORT_SYNTH_TWC     = 14,           // Synthetic TWC EP
+    PLX_SPEC_PORT_SYNTH_EN_EP   = 15,           // Synthetic Enabler EP
+    PLX_SPEC_PORT_SYNTH_NT      = 16,           // Synthetic NT 2.0 EP
+    PLX_SPEC_PORT_SYNTH_MPT     = 17,           // Synthetic MPT SAS controller EP
+    PLX_SPEC_PORT_SYNTH_GDMA    = 18,           // Synthetic gDMA EP
+    PLX_SPEC_PORT_INT_MGMT      = 19,           // iSSW internal management port
+} PLX_SPECIFIC_PORT_TYPE;
+
+// For compatibility
+typedef PLX_SPECIFIC_PORT_TYPE    PLX_NT_PORT_TYPE;
+
+
+// NT port configuration types
+typedef enum _PLX_NT_CONFIG_TYPE
+{
+    PLX_NT_CONFIG_TYPE_NONE     = 0,
+    PLX_NT_CONFIG_TYPE_LINK_DOWN,
+    PLX_NT_CONFIG_TYPE_STANDARD,
+    PLX_NT_CONFIG_TYPE_BACK_TO_BACK
+} PLX_NT_CONFIG_TYPE;
+
+
+// Non-transparent LUT flags
+typedef enum _PLX_NT_LUT_FLAG
+{
+    PLX_NT_LUT_FLAG_NONE        = 0,
+    PLX_NT_LUT_FLAG_NO_SNOOP    = (1 << 0),
+    PLX_NT_LUT_FLAG_READ        = (1 << 1),
+    PLX_NT_LUT_FLAG_WRITE       = (1 << 2)
+} PLX_NT_LUT_FLAG;
+
+
+// DMA control commands
+typedef enum _PLX_DMA_COMMAND
+{
+    DmaPause,
+    DmaPauseImmediate,
+    DmaResume,
+    DmaAbort
+} PLX_DMA_COMMAND;
+
+
+// DMA transfer direction
+typedef enum _PLX_DMA_DIR
+{
+    PLX_DMA_PCI_TO_LOC         = 0,                       // DMA PCI --> Local bus   (9000 DMA)
+    PLX_DMA_LOC_TO_PCI         = 1,                       // DMA Local bus --> PCI   (9000 DMA)
+    PLX_DMA_USER_TO_PCI        = PLX_DMA_PCI_TO_LOC,      // DMA User buffer --> PCI (8000 DMA)
+    PLX_DMA_PCI_TO_USER        = PLX_DMA_LOC_TO_PCI       // DMA PCI --> User buffer (8000 DMA)
+} PLX_DMA_DIR;
+
+
+// DMA Descriptor Mode
+typedef enum _PLX_DMA_DESCR_MODE
+{
+    PLX_DMA_MODE_BLOCK         = 0,         // DMA Block transfer mode
+    PLX_DMA_MODE_SGL           = 1,         // DMA SGL with descriptors off-chip
+    PLX_DMA_MODE_SGL_INTERNAL  = 2          // DMA SGL with descriptors on-chip
+} PLX_DMA_DESCR_MODE;
+
+
+// DMA Ring Delay Period
+typedef enum _PLX_DMA_RING_DELAY_TIME
+{
+    PLX_DMA_RING_DELAY_0       = 0,
+    PLX_DMA_RING_DELAY_1us     = 1,
+    PLX_DMA_RING_DELAY_2us     = 2,
+    PLX_DMA_RING_DELAY_8us     = 3,
+    PLX_DMA_RING_DELAY_32us    = 4,
+    PLX_DMA_RING_DELAY_128us   = 5,
+    PLX_DMA_RING_DELAY_512us   = 6,
+    PLX_DMA_RING_DELAY_1ms     = 7
+} PLX_DMA_RING_DELAY_TIME;
+
+
+// DMA Maximum Source & Destination Transfer Sizes
+typedef enum _PLX_DMA_MAX_TSIZE
+{
+    PLX_DMA_MAX_TSIZE_64B  = 0,
+    PLX_DMA_MAX_TSIZE_128B = 1,
+    PLX_DMA_MAX_TSIZE_256B = 2,
+    PLX_DMA_MAX_TSIZE_512B = 3,
+    PLX_DMA_MAX_TSIZE_1K   = 4,
+    PLX_DMA_MAX_TSIZE_2K   = 5,
+    PLX_DMA_MAX_TSIZE_4B   = 7,
+
+    // Legacy definitions may be removed in future
+    PLX_DMA_MAX_SRC_TSIZE_64B  = PLX_DMA_MAX_TSIZE_64B,
+    PLX_DMA_MAX_SRC_TSIZE_128B = PLX_DMA_MAX_TSIZE_128B,
+    PLX_DMA_MAX_SRC_TSIZE_256B = PLX_DMA_MAX_TSIZE_256B,
+    PLX_DMA_MAX_SRC_TSIZE_512B = PLX_DMA_MAX_TSIZE_512B,
+    PLX_DMA_MAX_SRC_TSIZE_1K   = PLX_DMA_MAX_TSIZE_1K,
+    PLX_DMA_MAX_SRC_TSIZE_2K   = PLX_DMA_MAX_TSIZE_2K,
+    PLX_DMA_MAX_SRC_TSIZE_4B   = PLX_DMA_MAX_TSIZE_4B
+} PLX_DMA_MAX_TSIZE;
+
+
+// Performance monitor control
+typedef enum _PLX_PERF_CMD
+{
+    PLX_PERF_CMD_START,
+    PLX_PERF_CMD_STOP,
+} PLX_PERF_CMD;
+
+
+// Used for device power state. Added for code compatability with Linux
+#if !defined(PLX_MSWINDOWS)
+    typedef enum _DEVICE_POWER_STATE
+    {
+        PowerDeviceUnspecified = 0,
+        PowerDeviceD0,
+        PowerDeviceD1,
+        PowerDeviceD2,
+        PowerDeviceD3,
+        PowerDeviceMaximum
+    } DEVICE_POWER_STATE;
+#endif
+
+
+// Properties of API access mode
+typedef struct _PLX_MODE_PROP
+{
+    union
+    {
+        struct
+        {
+            U16 I2cPort;
+            U16 SlaveAddr;
+            U32 ClockRate;
+        } I2c;
+
+        struct
+        {
+            U8    Port;
+            U32   ClockRate;
+            char *StrPath;
+        } Mdio;
+
+        struct
+        {
+            U8 Port;
+            U8 Baud;
+            U8 Cable;
+        } Sdb;
+
+        struct
+        {
+            U64 IpAddress;
+        } Tcp;
+    };
+} PLX_MODE_PROP;
+
+
+// PLX version information
+typedef struct _PLX_VERSION
+{
+    PLX_API_MODE ApiMode;
+
+    union
+    {
+        struct
+        {
+            U16 ApiLibrary;     // API library version
+            U16 Software;       // Software version
+            U16 Firmware;       // Firmware version
+            U16 Hardware;       // Hardware version
+            U16 SwReqByFw;      // Firmware requires software must be >= this version
+            U16 FwReqBySw;      // Software requires firmware must be >= this version
+            U16 ApiReqBySw;     // Software requires API interface must be >= this version
+            U32 Features;       // Bitmask of supported features
+        } I2c;
+    };
+} PLX_VERSION;
+
+
+// Chip features & port mask
+typedef struct _PEX_CHIP_FEAT
+{
+    U8 StnCount;                     // Supported station count
+    U8 PortsPerStn;                  // Max number of ports per station
+    U8 StnMask;                      // Bitmask of enabled stations
+    PEX_BITMASK_T( PortMask, 256 );  // Bitmask for ports and special types
+} PEX_CHIP_FEAT;
+
+
+// PCI Memory Structure
+typedef struct _PLX_PHYSICAL_MEM
+{
+    U64 UserAddr;                    // User-mode virtual address
+    U64 PhysicalAddr;                // Bus physical address
+    U64 CpuPhysical;                 // CPU physical address
+    U32 Size;                        // Size of the buffer
+} PLX_PHYSICAL_MEM;
+
+
+// PLX Driver Properties
+typedef struct _PLX_DRIVER_PROP
+{
+    U32  Version;                    // Driver version
+    char Name[16];                   // Driver name
+    char FullName[255];              // Full driver name
+    U8   bIsServiceDriver;           // Is service driver or PnP driver?
+    U64  AcpiPcieEcam;               // Base address of PCIe ECAM
+} PLX_DRIVER_PROP;
+
+
+// PCI BAR Properties
+typedef struct _PLX_PCI_BAR_PROP
+{
+    U64 BarValue;                    // Actual value in BAR
+    U64 Physical;                    // BAR Physical Address
+    U64 Size;                        // Size of BAR space
+    U32 Flags;                       // Additional BAR properties
+} PLX_PCI_BAR_PROP;
+
+
+// Used for getting the port properties and status
+typedef struct _PLX_PORT_PROP
+{
+    U8  PortType;                    // Port configuration
+    U8  PortNumber;                  // Internal port number
+    U8  LinkWidth;                   // Negotiated port link width
+    U8  MaxLinkWidth;                // Max link width device is capable of
+    U8  LinkSpeed;                   // Negotiated link speed
+    U8  MaxLinkSpeed;                // Max link speed device is capable of
+    U16 MaxReadReqSize;              // Max read request size allowed
+    U16 MaxPayloadSize;              // Max payload size setting
+    U16 MaxPayloadSupported;         // Max payload size supported by device
+    U8  bNonPcieDevice;              // Flag whether device is a PCIe device
+} PLX_PORT_PROP;
+
+
+// Used for getting the multi-host switch properties
+typedef struct _PLX_MULTI_HOST_PROP
+{
+    U8  SwitchMode;                  // Current switch mode
+    U16 VS_EnabledMask;              // Bit for each enabled Virtual Switch
+    U8  VS_UpstreamPortNum[8];       // Upstream port number of each Virtual Switch
+    U32 VS_DownstreamPorts[8];       // Downstream ports associated with a Virtual Switch
+    U8  bIsMgmtPort;                 // Is selected device management port
+    U8  bMgmtPortActiveEn;           // Is active management port enabled
+    U8  MgmtPortNumActive;           // Active management port
+    U8  bMgmtPortRedundantEn;        // Is redundant management port enabled
+    U8  MgmtPortNumRedundant;        // Redundant management port
+} PLX_MULTI_HOST_PROP;
+
+
+// SPI flash properties
+typedef struct _PEX_SPI_OBJ
+{
+    U32 IsValidTag;                  // Magic number to determine validity
+    U8  Flags;                       // Additional flags
+    U8  ChipSel;                     // Chip select to access
+    U8  IoMode;                      // I/O moode to use
+    U8  PageSize;                    // Page size in power of 2
+    U8  SectorsCount;                // Sector count in power of 2
+    U8  SectorSize;                  // Sector size in  power of 2
+    U8  MfgID;                       // Manufacturer ID
+    U16 DeviceId;                    // Device-reported ID
+    U32 CtrlBaseAddr;                // Address/offset of SPI controller registers
+    U32 MmapAddr;                    // AXI mem-mapped address to flash (optional)
+} PEX_SPI_OBJ;
+
+
+// PCI Device Key Identifier
+typedef struct _PLX_DEVICE_KEY
+{
+    U32 IsValidTag;                  // Magic number to determine validity
+    U8  domain;                      // Physical device location
+    U8  bus;
+    U8  slot;
+    U8  function;
+    U16 VendorId;                    // Device Identifier
+    U16 DeviceId;
+    U16 SubVendorId;
+    U16 SubDeviceId;
+    U8  Revision;
+    U16 PlxChip;                     // PLX chip type
+    U16 ChipID;                      // Chip ID (if reported)
+    U8  PlxRevision;                 // PLX chip revision
+    U8  PlxFamily;                   // PLX chip family
+    U8  ApiIndex;                    // Used internally by the API
+    U16 DeviceNumber;                // Used internally by device drivers
+    U8  ApiMode;                     // Mode API uses to access device
+    U8  PlxPort;                     // PLX port number of device
+    U8  PlxPortType;                 // PLX-specific port type (NT/DMA/Host/etc)
+    U8  NTPortNum;                   // If NT port exists, store NT port number
+    U8  DeviceMode;                  // Device mode used internally by API
+    U32 ApiInternal[2];              // Reserved for internal PLX API use
+} PLX_DEVICE_KEY;
+
+
+// PLX Device Object Structure
+typedef struct _PLX_DEVICE_OBJECT
+{
+    U32               IsValidTag;    // Magic number to determine validity
+    PLX_DEVICE_KEY    Key;           // Device location key identifier
+    PLX_DRIVER_HANDLE hDevice;       // Handle to driver
+    PLX_PCI_BAR_PROP  PciBar[6];     // PCI BAR properties
+    U64               PciBarVa[6];   // For PCI BAR user-mode BAR mappings
+    U8                BarMapRef[6];  // BAR map count used by API
+    PLX_PHYSICAL_MEM  CommonBuffer;  // Used to store common buffer information
+    U64               PrivateData[4];// Private storage for user application
+} PLX_DEVICE_OBJECT;
+
+
+// PLX Notification Object
+typedef struct _PLX_NOTIFY_OBJECT
+{
+    U32 IsValidTag;                  // Magic number to determine validity
+    U64 pWaitObject;                 // -- INTERNAL -- Wait object used by the driver
+    U64 hEvent;                      // User event handle (HANDLE can be 32 or 64 bit)
+} PLX_NOTIFY_OBJECT;
+
+
+// PLX Interrupt Structure
+typedef struct _PLX_INTERRUPT
+{
+    U32 Doorbell;                    // Up to 32 doorbells
+    U8  PciMain                :1;
+    U8  PciAbort               :1;
+    U8  LocalToPci             :2;   // Local->PCI interrupts 1 & 2
+    U8  DmaDone                :4;   // DMA channel 0-3 interrupts
+    U8  DmaPauseDone           :4;
+    U8  DmaAbortDone           :4;
+    U8  DmaImmedStopDone       :4;
+    U8  DmaInvalidDescr        :4;
+    U8  DmaError               :4;
+    U8  MuInboundPost          :1;
+    U8  MuOutboundPost         :1;
+    U8  MuOutboundOverflow     :1;
+    U8  TargetRetryAbort       :1;
+    U8  Message                :4;   // 6000 NT 0-3 message interrupts
+    U8  SwInterrupt            :1;
+    U8  ResetDeassert          :1;
+    U8  PmeDeassert            :1;
+    U8  GPIO_4_5               :1;   // 6000 NT GPIO 4/5 interrupt
+    U8  GPIO_14_15             :1;   // 6000 NT GPIO 14/15 interrupt
+    U8  NTV_LE_Correctable     :1;   // 8000 NT Virtual - Link-side error interrupts
+    U8  NTV_LE_Uncorrectable   :1;
+    U8  NTV_LE_LinkStateChange :1;
+    U8  NTV_LE_UncorrErrorMsg  :1;
+} PLX_INTERRUPT;
+
+
+// DMA Channel Properties Structure
+typedef struct _PLX_DMA_PROP
+{
+    // 8000 DMA properties
+    U8  CplStatusWriteBack  :1;
+    U8  DescriptorMode      :2;
+    U8  DescriptorPollMode  :1;
+    U8  RingHaltAtEnd       :1;
+    U8  RingWrapDelayTime   :3;
+    U8  RelOrderDescrRead   :1;
+    U8  RelOrderDescrWrite  :1;
+    U8  RelOrderDataReadReq :1;
+    U8  RelOrderDataWrite   :1;
+    U8  NoSnoopDescrRead    :1;
+    U8  NoSnoopDescrWrite   :1;
+    U8  NoSnoopDataReadReq  :1;
+    U8  NoSnoopDataWrite    :1;
+    U8  MaxSrcXferSize      :3;
+    U8  MaxDestWriteSize    :3;
+    U8  TrafficClass        :3;
+    U8  MaxPendingReadReq   :6;
+    U8  DescriptorPollTime;
+    U8  MaxDescriptorFetch;
+    U16 ReadReqDelayClocks;
+
+    // 9000 DMA properties
+    U8  ReadyInput          :1;
+    U8  Burst               :1;
+    U8  BurstInfinite       :1;
+    U8  SglMode             :1;
+    U8  DoneInterrupt       :1;
+    U8  RouteIntToPci       :1;
+    U8  ConstAddrLocal      :1;
+    U8  WriteInvalidMode    :1;
+    U8  DemandMode          :1;
+    U8  EnableEOT           :1;
+    U8  FastTerminateMode   :1;
+    U8  ClearCountMode      :1;
+    U8  DualAddressMode     :1;
+    U8  EOTEndLink          :1;
+    U8  ValidMode           :1;
+    U8  ValidStopControl    :1;
+    U8  LocalBusWidth       :2;
+    U8  WaitStates          :4;
+} PLX_DMA_PROP;
+
+
+// DMA Transfer Parameters
+typedef struct _PLX_DMA_PARAMS
+{
+    U64 UserVa;                     // User buffer virtual address
+    U64 AddrSource;                 // Source address      (8000 DMA)
+    U64 AddrDest;                   // Destination address (8000 DMA)
+    U64 PciAddr;                    // PCI address         (9000 DMA)
+    U32 LocalAddr;                  // Local bus address   (9000 DMA)
+    U32 ByteCount;                  // Number of bytes to transfer
+    U8  Direction;                  // Direction of transfer (Local<->PCI, User<->PCI) (9000 DMA)
+    U8  bConstAddrSrc   :1;         // Constant source PCI address?      (8000 DMA)
+    U8  bConstAddrDest  :1;         // Constant destination PCI address? (8000 DMA)
+    U8  bForceFlush     :1;         // Force DMA to flush write on final descriptor (8000 DMA)
+    U8  bIgnoreBlockInt :1;         // For block mode only, do not enable DMA done interrupt
+} PLX_DMA_PARAMS;
+
+
+// Performance properties
+typedef struct _PLX_PERF_PROP
+{
+    U32 IsValidTag;   // Magic number to determine validity
+
+    // Chip properties
+    U8  PlxFamily;
+
+    // Port properties
+    U8  PortNumber;
+    U8  LinkWidth;
+    U8  LinkSpeed;
+    U8  Station;
+    U8  StationPort;
+
+    // Ingress counters
+    U32 IngressPostedHeader;
+    U32 IngressPostedDW;
+    U32 IngressNonpostedHdr;
+    U32 IngressNonpostedDW;
+    U32 IngressCplHeader;
+    U32 IngressCplDW;
+    U32 IngressDllp;
+
+    // Egress counters
+    U32 EgressPostedHeader;
+    U32 EgressPostedDW;
+    U32 EgressNonpostedHdr;
+    U32 EgressNonpostedDW;
+    U32 EgressCplHeader;
+    U32 EgressCplDW;
+    U32 EgressDllp;
+
+    // Storage for previous counter values
+
+    // Previous Ingress counters
+    U32 Prev_IngressPostedHeader;
+    U32 Prev_IngressPostedDW;
+    U32 Prev_IngressNonpostedHdr;
+    U32 Prev_IngressNonpostedDW;
+    U32 Prev_IngressCplHeader;
+    U32 Prev_IngressCplDW;
+    U32 Prev_IngressDllp;
+
+    // Previous Egress counters
+    U32 Prev_EgressPostedHeader;
+    U32 Prev_EgressPostedDW;
+    U32 Prev_EgressNonpostedHdr;
+    U32 Prev_EgressNonpostedDW;
+    U32 Prev_EgressCplHeader;
+    U32 Prev_EgressCplDW;
+    U32 Prev_EgressDllp;
+} PLX_PERF_PROP;
+
+
+// Performance statistics
+typedef struct _PLX_PERF_STATS
+{
+    S64         IngressTotalBytes;              // Total bytes including overhead
+    long double IngressTotalByteRate;           // Total byte rate
+    S64         IngressCplAvgPerReadReq;        // Average number of completion TLPs for read requests
+    S64         IngressCplAvgBytesPerTlp;       // Average number of bytes per completion TLPs
+    S64         IngressPayloadReadBytes;        // Payload bytes read (Completion TLPs)
+    S64         IngressPayloadReadBytesAvg;     // Average payload bytes for reads (Completion TLPs)
+    S64         IngressPayloadWriteBytes;       // Payload bytes written (Posted TLPs)
+    S64         IngressPayloadWriteBytesAvg;    // Average payload bytes for writes (Posted TLPs)
+    S64         IngressPayloadTotalBytes;       // Payload total bytes
+    double      IngressPayloadAvgPerTlp;        // Payload average size per TLP
+    long double IngressPayloadByteRate;         // Payload byte rate
+    long double IngressLinkUtilization;         // Total link utilization
+
+    S64         EgressTotalBytes;               // Total byte including overhead
+    long double EgressTotalByteRate;            // Total byte rate
+    S64         EgressCplAvgPerReadReq;         // Average number of completion TLPs for read requests
+    S64         EgressCplAvgBytesPerTlp;        // Average number of bytes per completion TLPs
+    S64         EgressPayloadReadBytes;         // Payload bytes read (Completion TLPs)
+    S64         EgressPayloadReadBytesAvg;      // Average payload bytes for reads (Completion TLPs)
+    S64         EgressPayloadWriteBytes;        // Payload bytes written (Posted TLPs)
+    S64         EgressPayloadWriteBytesAvg;     // Average payload bytes for writes (Posted TLPs)
+    S64         EgressPayloadTotalBytes;        // Payload total bytes
+    double      EgressPayloadAvgPerTlp;         // Payload average size per TLP
+    long double EgressPayloadByteRate;          // Payload byte rate
+    long double EgressLinkUtilization;          // Total link utilization
+} PLX_PERF_STATS;
+
+
+
+// Restore previous pack value
+#pragma pack( pop )
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/Plx_sysdep.h b/Plxlibrary/Plx_sysdep.h
new file mode 100755
index 0000000..18b027c
--- /dev/null
+++ b/Plxlibrary/Plx_sysdep.h
@@ -0,0 +1,490 @@
+#ifndef _PLX_SYSDEP_H_
+#define _PLX_SYSDEP_H_
+
+/*******************************************************************************
+ * Copyright 2013-2019 Broadcom Inc
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *      Plx_sysdep.h
+ *
+ * Description:
+ *
+ *      This file is provided to support compatible code between different
+ *      Linux kernel versions.
+ *
+ * Revision History:
+ *
+ *      04-01-19 : PCI/PCIe SDK v8.00
+ *
+ *****************************************************************************/
+
+
+#ifndef LINUX_VERSION_CODE
+    #include <linux/version.h>
+#endif
+
+
+// Only allow 2.6.18 and higher kernels
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
+    #error "ERROR: Linux kernel versions prior to v2.6.18 not supported"
+#endif
+
+
+
+
+/***********************************************************
+ * IORESOURCE_MEM_64
+ *
+ * This flag specifies whether a PCI BAR space is 64-bit. The
+ * definition wasn't added until 2.6.31.
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
+    #define IORESOURCE_MEM_64           0x00100000
+#endif
+
+
+
+
+/***********************************************************
+ * VM_RESERVED
+ *
+ * This flag was removed starting with 3.7. The recommended
+ * replacement is a combination of two flags.
+ **********************************************************/
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
+    #define VM_RESERVED                 (VM_DONTEXPAND | VM_DONTDUMP)
+#endif
+
+
+
+
+/***********************************************************
+ * INIT_WORK & INIT_DELAYED_WORK
+ *
+ * This macro initializes a work structure with the function
+ * to call.  In kernel 2.6.20, the 3rd parameter was removed.
+ * It used to be the parameter to the function, but now, the
+ * function is called with a pointer to the work_struct itself.
+ * INIT_DELAYED_WORK was introduced to init the delayed_work struct.
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
+    #define PLX_INIT_WORK                     INIT_WORK
+    // Red Hat pre-defines this
+    #if !defined(RED_HAT_LINUX_KERNEL)
+        #define INIT_DELAYED_WORK             INIT_WORK
+    #endif
+#else
+    #define PLX_INIT_WORK(work, func, data)   INIT_WORK((work), (func))
+#endif
+
+
+
+
+/***********************************************************
+ * ioremap_prot
+ *
+ * This function is supported after 2.6.27 only one some
+ * architectures, like x86 & PowerPC. Other architectures
+ * added support for it in later kernels. For platforms
+ * that support it, HAVE_IOREMAP_PROT is expected defined.
+ * SDK drivers use the function for probing ACPI tables. In
+ * newer kernels, calls to ioremap() for ACPI locations may
+ * report errors if default flags conflict with kernel mappings.
+ **********************************************************/
+#if !defined(CONFIG_HAVE_IOREMAP_PROT)
+    // Revert to ioremap() for unsupported architectures
+    #define ioremap_prot(addr,size,flags)     ioremap((addr), (size))
+#endif
+
+
+
+
+/***********************************************************
+ * pgprot_writecombine
+ *
+ * This function is not supported on all platforms. There is
+ * a standard definition for it starting with 2.6.29.
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29))
+    #define pgprot_writecombine               pgprot_noncached
+#endif
+
+
+
+
+/***********************************************************
+ * access_ok
+ *
+ * access_ok() removed type param in 5.0
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,0,0))
+    #define Plx_access_ok                     access_ok
+#else
+    #define Plx_access_ok(type,addr,size)     access_ok( (addr),(size) )
+#endif
+
+
+
+
+/***********************************************************
+ * sema_init / init_MUTEX
+ *
+ * init_MUTEX replaced by sema_init starting with 2.6.26
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26))
+    #define Plx_sema_init(sem, n)             init_MUTEX( (sem) )
+#else
+    #define Plx_sema_init                     sema_init
+#endif
+
+
+
+
+/***********************************************************
+ * flush_work
+ *
+ * Flush work queue function not added until 2.6.27
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27))
+    #define Plx_flush_work(x)
+#else
+    #define Plx_flush_work                    flush_work
+#endif
+
+
+
+
+/***********************************************************
+ * PLX_DPC_PARAM
+ *
+ * In kernel 2.6.20, the parameter to a work queue function
+ * was made to always be a pointer to the work_struct itself.
+ * In previous kernels, this was always a VOID*.  Since
+ * PLX drivers use work queue functions for the DPC/bottom-half
+ * processing, the parameter had to be changed.  For cleaner
+ * source code, the definition PLX_DPC_PARAM is used and is
+ * defined below.
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
+    #define PLX_DPC_PARAM      VOID
+#else
+    #define PLX_DPC_PARAM      struct work_struct
+#endif
+
+
+
+
+/***********************************************************
+ * pci_get_domain_bus_and_slot not added until 2.6.33
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))
+    #define Plx_pci_get_domain_bus_and_slot(d,b,df)    pci_get_bus_and_slot( b, df )
+#else
+    #define Plx_pci_get_domain_bus_and_slot            pci_get_domain_bus_and_slot
+#endif
+
+
+
+
+/***********************************************************
+ * pci_enable_msi/pci_enable_msix deprecated
+ *
+ * The pci_*_msi/msix MSI functions are deprecated as of
+ * kernel 4.8. A new set of PCI subsystem functions have
+ * replaced them.
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0))
+
+    #define Plx_pci_enable_msi          pci_enable_msi
+    #define Plx_pci_disable_msi         pci_disable_msi
+    #define Plx_pci_enable_msix         pci_enable_msix
+    #define Plx_pci_disable_msix        pci_disable_msix
+
+#else
+
+    #define Plx_pci_enable_msi( pdev )  pci_alloc_irq_vectors( (pdev), 1, 1, PCI_IRQ_MSI )
+    #define Plx_pci_disable_msi         pci_free_irq_vectors
+    #define Plx_pci_disable_msix        pci_free_irq_vectors
+
+    #define Plx_pci_enable_msix(pdev,entries,nvec)                       \
+        ({                                                               \
+            int _rc;                                                     \
+            int _idx;                                                    \
+                                                                         \
+            /* Attempt to allocate MSI-X vectors */                      \
+            _rc = pci_alloc_irq_vectors(                                 \
+                      (pdev), (nvec), (nvec), PCI_IRQ_MSIX );            \
+            if (_rc == (nvec))                                           \
+            {                                                            \
+                /* Set successful return value */                        \
+                _rc = 0;                                                 \
+                                                                         \
+                /* Fill in the vector table */                           \
+                for (_idx = 0; _idx < (nvec); _idx++)                    \
+                {                                                        \
+                    (entries)[_idx].vector =                             \
+                        pci_irq_vector( (pdev), (entries)[_idx].entry ); \
+                }                                                        \
+            }                                                            \
+                                                                         \
+            _rc;                                                         \
+        })
+
+#endif
+
+
+
+
+/***********************************************************
+ * kmap_atomic/kunmap_atomic - 2nd parameter removed in 2.6.37
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37))
+    #define Plx_kmap_atomic                  kmap_atomic
+    #define Plx_kunmap_atomic                kunmap_atomic
+#else
+    #define Plx_kmap_atomic(page,kmtype)     kmap_atomic( (page) )
+    #define Plx_kunmap_atomic(page,kmtype)   kunmap_atomic( (page) )
+#endif
+
+
+
+
+/***********************************************************
+ * 'secondary' & 'subordinate' fields removed from 'struct pci_bus'
+ * in 3.6 & replaced with start/end fields in a 'struct resource'.
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0))
+    #define Plx_STRUCT_PCI_BUS_SEC(pbus)   (pbus)->secondary
+    #define Plx_STRUCT_PCI_BUS_SUB(pbus)   (pbus)->subordinate
+#else
+    #define Plx_STRUCT_PCI_BUS_SEC(pbus)   (pbus)->busn_res.start
+    #define Plx_STRUCT_PCI_BUS_SUB(pbus)   (pbus)->busn_res.end
+#endif
+
+
+
+
+/***********************************************************
+ * skb_frag_struct "page" field changed from pointer to
+ * a page pointer within a structure in 3.2.0
+ **********************************************************/
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0))
+    #define Plx_SKB_FRAG_STRUCT_PAGE(frag)   (frag)->page
+#else
+    #define Plx_SKB_FRAG_STRUCT_PAGE(frag)   (frag)->page.p
+#endif
+
+
+
+
+/***********************************************************
+ * pcie_cap field in pci_dev   - Added by 2.6.38
+ *
+ * The pci_dev structure has a pcie_cap field to report the
+ * device's PCIe capability (10h) starting offset.
+ * This field is was also added to updated RedHat kernels.
+ **********************************************************/
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || \
+    ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)) && defined(RED_HAT_LINUX_KERNEL))
+    #define Plx_pcie_cap(pDev)      ((pDev)->pcie_cap)
+#else
+    #define Plx_pcie_cap(pDev)      pci_find_capability( (pDev), 0x10 )
+#endif
+
+
+
+
+/***********************************************************
+ * is_virtfn field in pci_dev   - Added in 2.6.30
+ * pci_physfn                   - Added by 2.6.35
+ *
+ * For SR-IOV devices, there is an 'is_virtfn' field in the
+ * pci_dev structure to report whether the device is a VF. This
+ * field is was also added to updated RedHat kernels.
+ *
+ * pci_physfn returns the parent PF of a VF; otherwise, returns
+ * the passed device.
+ ***********************************************************/
+#if defined(CONFIG_PCI_IOV) && \
+     ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) || \
+     ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)) && defined(RED_HAT_LINUX_KERNEL)))
+    #define Plx_pcie_is_virtfn(pDev)    ((pDev)->is_virtfn)
+
+    #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35))
+        #define Plx_pci_physfn(pDev)       \
+            ({                             \
+               struct pci_dev *_pDev;      \
+                                           \
+               if (pDev->is_virtfn)        \
+                   _pDev = (pDev->physfn); \
+               else                        \
+                   _pDev = pDev;           \
+               _pDev;                      \
+            })
+    #else
+        #define Plx_pci_physfn          pci_physfn
+    #endif
+#else
+    #define Plx_pcie_is_virtfn(pDev)    (FALSE)
+    #define Plx_pci_physfn(pDev)        (pDev)
+#endif
+
+
+
+
+/***********************************************************
+ * readq / writeq
+ *
+ * These functions are used to perform 64-bit accesses to
+ * I/O memory.  They are not defined for all architectures.
+ * For x86 32-bit, they were added in 2.6.29.
+ *
+ * NOTE: This is still incomplete for non-x86 32-bit architectures
+ *       where readq/writeq are not yet defined.
+ **********************************************************/
+#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)) && defined(CONFIG_X86_32))
+    // x86 64-bit I/O access functions
+    static inline __u64 readq(const volatile void __iomem *addr)
+    {
+        const volatile u32 __iomem *p = addr;
+        u64 value;
+
+        value  = readl(p);
+        value += ((u64)readl(p + 1) << 32);
+
+        return value;
+    }
+
+    static inline void writeq(__u64 val, volatile void __iomem *addr)
+    {
+        writel(val, addr);
+        writel(val >> 32, addr+4);
+    }
+
+#elif !defined(CONFIG_64BIT) && !defined(CONFIG_X86_32)
+    // Revert to 32-bit accesses for non-x86/x64 platforms
+    #define readq                   readl
+    #define writeq                  writel
+#endif
+
+
+
+
+/***********************************************************
+ * get_user_pages
+ *
+ * Parameters to this function changed as follows:
+ *   4.6: Removed first two params (curr task & task's mem-manage struct)
+ *   4.9: Replaced write & force params with a single gup_flags param
+ **********************************************************/
+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
+    #define Plx_get_user_pages(start, nr_pages, gup_flags, pages, vmas) \
+            (                                           \
+                get_user_pages(                         \
+                    current,                            \
+                    current->mm,                        \
+                    (start),                            \
+                    (nr_pages),                         \
+                    ((gup_flags) & FOLL_WRITE) ? 1 : 0, \
+                    0,                                  \
+                    (pages),                            \
+                    (vmas)                              \
+                    )                                   \
+            )
+#elif LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0)
+    #define Plx_get_user_pages(start, nr_pages, gup_flags, pages, vmas) \
+            (                                           \
+                get_user_pages(                         \
+                    (start),                            \
+                    (nr_pages),                         \
+                    ((gup_flags) & FOLL_WRITE) ? 1 : 0, \
+                    0,                                  \
+                    (pages),                            \
+                    (vmas)                              \
+                    )                                   \
+            )
+#else
+    #define Plx_get_user_pages          get_user_pages
+#endif
+
+
+
+
+/***********************************************************
+ * dma_set_coherent_mask / pci_set_consistent_dma_mask
+ *
+ * This function is used to set the mask for coherent/consistent
+ * DMA buffer allocations.  Prior to 2.6.34, the function is
+ * pci_set_consistent_dma_mask.  It is now dma_set_coherent_mask.
+ * The first parameter has also been changed from pci_dev
+ * structure to the dev structure found in pci_dev.
+ **********************************************************/
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)
+    #define Plx_dma_set_coherent_mask(pdx, mask) \
+            (                                    \
+                pci_set_consistent_dma_mask(     \
+                    (pdx)->pPciDevice,           \
+                    (mask)                       \
+                    )                            \
+            )
+#else
+    #define Plx_dma_set_coherent_mask(pdx, mask) \
+            (                                    \
+                dma_set_coherent_mask(           \
+                    &((pdx)->pPciDevice->dev),   \
+                    (mask)                       \
+                    )                            \
+            )
+#endif
+
+
+
+
+/***********************************************************
+ * DMA_BIT_MASK
+ *
+ * This macro is used to specify bit masks (e.g dma_set_mask).
+ * It was introduced in 2.6.24
+ **********************************************************/
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
+    #define PLX_DMA_BIT_MASK(n)         (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
+#else
+    #define PLX_DMA_BIT_MASK            DMA_BIT_MASK
+#endif
+
+
+
+#endif  // _PLX_SYSDEP_H_
diff --git a/Plxlibrary/SdbComPort.h b/Plxlibrary/SdbComPort.h
new file mode 100755
index 0000000..0b4f468
--- /dev/null
+++ b/Plxlibrary/SdbComPort.h
@@ -0,0 +1,171 @@
+#ifndef __SDB_COM_PORT_H
+#define __SDB_COM_PORT_H
+
+/*******************************************************************************
+ * Copyright 2013-2019 Broadcom, Inc
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/*******************************************************************************
+ *
+ * File Name:
+ *
+ *     SdbComPort.h
+ *
+ * Description:
+ *
+ *     Header file for SDB COM port interface functions
+ *
+ * Revision History:
+ *
+ *     09-01-19: PCI/PCIe SDK v8.10
+ *
+ ******************************************************************************/
+
+
+#include "PlxIoctl.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/******************************************
+ *             Definitions
+ ******************************************/
+// OS-specific prefix for COM/TTY port name
+#if defined(PLX_MSWINDOWS)
+    #define SDB_OS_COM_PORT_UART        "\\\\.\\COM"
+    #define SDB_OS_COM_PORT_USB         SDB_OS_COM_PORT_UART
+    #define SDB_OS_BAUD_19200           CBR_19200
+    #define SDB_OS_BAUD_115200          CBR_115200
+#elif defined(PLX_LINUX)
+    #define SDB_OS_COM_PORT_UART        "/dev/ttyS"
+    #define SDB_OS_COM_PORT_USB         "/dev/ttyUSB"
+    #define SDB_OS_BAUD_19200           B19200
+    #define SDB_OS_BAUD_115200          B115200
+#endif
+
+#define SDB_MAX_ATTEMPTS                2            // Max num of attempts if failure
+#define SDB_NEEDS_INIT_CMD              (0xFFFFFFFE) // Needs initial sync command
+#define SDB_NEXT_READ_OFFSET_INIT       (0xFFFFFFFF) // Init offset to force full read cmd
+
+// SDB command & reply sizes
+#define SDB_READ_CMD_LEN                (1 + 1 + 4 + 1)     // Cmd + size + addr + end
+#define SDB_READ_NEXT_CMD_LEN           (1 + 1)             // Cmd + end
+#define SDB_READ_REPLY_LEN              (4 + 1)             // 4B data + ACK('%')
+#define SDB_WRITE_CMD_LEN               (1 + 1 + 4 + 4 + 1) // Cmd + size + addr + data + end
+#define SDB_WRITE_REPLY_LEN             (1)                 // 1B ACK('%')
+
+// SDB binary commands
+#define SDB_CMD_READ                    'G'
+#define SDB_CMD_READ_NEXT               'N'
+#define SDB_CMD_WRITE                   'P'
+#define SDB_CMD_END                     '\n'
+#define SDB_CMD_ACK                     '%'
+#define SDB_CMD_ERROR                   'E'
+#define SDB_CMD_INIT                    "%\n"
+
+
+
+
+/******************************************
+ *      Device Selection Functions
+ *****************************************/
+PLX_STATUS
+Sdb_DeviceOpen(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+PLX_STATUS
+Sdb_DeviceClose(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+PLX_STATUS
+Sdb_DeviceFindEx(
+    PLX_DEVICE_KEY *pKey,
+    U16             DeviceNumber,
+    PLX_MODE_PROP  *pModeProp
+    );
+
+
+/******************************************
+ *      MDIO Private Support Functions
+ *****************************************/
+PLX_STATUS
+Sdb_Driver_Connect(
+    PLX_DEVICE_OBJECT *pDevice,
+    PLX_MODE_PROP     *pModeProp
+    );
+
+BOOLEAN
+Sdb_Sync_Connection(
+    PLX_DEVICE_OBJECT *pDevice
+    );
+
+S32
+Sdb_Dispatch_IoControl(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                IoControlCode,
+    PLX_PARAMS        *pIoBuffer,
+    U32                Size
+    );
+
+
+/******************************************
+ * Device-specific Register Access Functions
+ *****************************************/
+U32
+Sdb_PlxRegisterRead(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    PLX_STATUS        *pStatus,
+    BOOLEAN            bAdjustForPort,
+    U16                bRetryOnError
+    );
+
+PLX_STATUS
+Sdb_PlxRegisterWrite(
+    PLX_DEVICE_OBJECT *pDevice,
+    U32                offset,
+    U32                value,
+    BOOLEAN            bAdjustForPort
+    );
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Plxlibrary/SpiFlash.h b/Plxlibrary/SpiFlash.h
new file mode 100755
index 0000000..9eab2c0
--- /dev/null
+++ b/Plxlibrary/SpiFlash.h
@@ -0,0 +1,192 @@
+#ifndef __SPI_FLASH_H
+#define __SPI_FLASH_H
+
+/*******************************************************************************
+ * Copyright 2013-2020 Broadcom Inc
+ * Copyright (c) 2009 to 2012 PLX Technology Inc.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directorY of this source tree, or the
+ * BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:
+ *
+ *     SpiFlash.h
+ *
+ * Description:
+ *
+ *     SPI flash access functions
+ *
+ * Revision:
+ *
+ *     03-01-20 : PCI/PCIe SDK v8.10
+ *
+ ******************************************************************************/
+
+
+#include "PlxApiDirect.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+/******************************************
+ *             Definitions
+ ******************************************/
+
+#define SPI_REG_ADDR( ptrSpi, offset )      ((ptrSpi)->CtrlBaseAddr + (offset))
+#define SPI_MAX_CMD_LEN                     (1 + 4) // 1B cmd + 4B addr
+
+// Max time to wait until controller is ready
+#define SPI_MAX_WAIT_CTRL_READY_MS          (1000)
+
+// PBAM SPI registers
+#define PEX_REG_SPI_MANUAL_IO_MODE          0x7C
+#define PEX_REG_SPI_MANUAL_RD_DATA          0x78
+#define PEX_REG_SPI_MANUAL_WR_DATA          0x80
+#define PEX_REG_SPI_MANUAL_CTRL_STAT        0x84
+
+// SPI flash command codes
+#define SPI_FLASH_CMD_READ_ID_DEPRECATED    0x90
+#define SPI_FLASH_CMD_READ_ID_CFI           0x9F
+#define SPI_FLASH_CMD_ERASE_ALL             0x60
+#define SPI_FLASH_CMD_3B_ERASE_SECTOR       0xD8
+#define SPI_FLASH_CMD_4B_ERASE_SECTOR       0xDC
+#define SPI_FLASH_CMD_3B_READ               0x03
+#define SPI_FLASH_CMD_3B_READ_DUAL_IO       0xBB
+#define SPI_FLASH_CMD_3B_READ_QUAD_IO       0xEB
+#define SPI_FLASH_CMD_4B_READ               0x13
+#define SPI_FLASH_CMD_3B_WRITE              0x02
+#define SPI_FLASH_CMD_3B_WRITE_QUAD_IO      0x32
+#define SPI_FLASH_CMD_4B_WRITE              0x12
+#define SPI_FLASH_CMD_WRITE_ENABLE          0x06
+#define SPI_FLASH_CMD_WRITE_DISABLE         0x04
+#define SPI_FLASH_CMD_RD_STATUS_REG_1       0x05
+
+// SPI command additional flags
+#define SPI_CMD_FLAGS_NONE                  0
+#define SPI_CMD_FLAGS_OP_MORE_CMDS          (1 << 0)  // More commands coming for operation
+#define SPI_CMD_FLAGS_OP_MORE_DATA          (1 << 1)  // More data coming for operation
+
+// SPI Manual control reg fields
+#define SPI_MAN_CTRL_LEN_SHIFT              0
+#define SPI_MAN_CTRL_CS_SHIFT               7
+#define SPI_MAN_CTRL_LAST_MASK              ((U32)1 << 11)
+#define SPI_MAN_CTRL_WRITE_OP_MASK          ((U32)1 << 12)
+#define SPI_MAN_CTRL_ATOMIC_OP_MASK         ((U32)1 << 14)
+#define SPI_MAN_CTRL_VALID_MASK             ((U32)1 << 16)
+
+// Status register 1
+#define SPI_FLASH_REG_SR1_WRITE_IN_PROG     (1 << 0)
+#define SPI_FLASH_REG_SR1_WRITE_EN_LATCH    (1 << 1)
+#define SPI_FLASH_REG_SR1_BLOCK_PROT_0      (1 << 2)
+#define SPI_FLASH_REG_SR1_BLOCK_PROT_1      (1 << 3)
+#define SPI_FLASH_REG_SR1_BLOCK_PROT_2      (1 << 4)
+#define SPI_FLASH_REG_SR1_ERASE_ERR         (1 << 5)
+#define SPI_FLASH_REG_SR1_PROG_ERR          (1 << 6)
+#define SPI_FLASH_REG_SR1_SR_WRITE_DIS      (1 << 7)
+
+
+
+
+/******************************************
+ *     SPI Flash Functions
+ *****************************************/
+PLX_STATUS
+Spi_FlashPropGet(
+    PLX_DEVICE_OBJECT *PtrDev,
+    U8                 ChipSel,
+    PEX_SPI_OBJ       *PtrSpi
+    );
+
+PLX_STATUS
+Spi_Erase(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi,
+    U32                StartOffset,
+    U8                 BoolWaitComplete
+    );
+
+PLX_STATUS
+Spi_ReadBuffer(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi,
+    U32                StartOffset,
+    U8               *PtrRxBuff,
+    U32                SizeRx
+    );
+
+PLX_STATUS
+Spi_WriteBuffer(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi,
+    U32                StartOffset,
+    U8                *PtrTxBuff,
+    U32                SizeTx
+    );
+
+PLX_STATUS
+Spi_GetStatus(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi
+    );
+
+
+/******************************************
+ *      Support Functions
+ *****************************************/
+PLX_STATUS
+Spi_CmdSendAndReply(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi,
+    U8                 Flags,
+    U8                *PtrDataTx,
+    U32                SizeTx,
+    U8                *PtrDataRx,
+    U32                SizeRx
+    );
+
+PLX_STATUS
+Spi_WaitControllerReady(
+    PLX_DEVICE_OBJECT *PtrDev,
+    PEX_SPI_OBJ       *PtrSpi
+    );
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/Test/MainWindow.cpp b/Test/MainWindow.cpp
index f32db8d..2b2f2dd 100755
--- a/Test/MainWindow.cpp
+++ b/Test/MainWindow.cpp
@@ -7,12 +7,11 @@ MainWindow::MainWindow(QWidget* parent)
     : QMainWindow(parent)
     , ui(new Ui::MainWindow)
 {
-//        system("sudo PlxSdk/Bin/Plx_load 9054 d");
-//        system("echo jangal28 | sudo -S gedit");
-
-
     ui->setupUi(this);
     connect(&_honaAPI, &HonaAPI::honaDataResult, this, &MainWindow::honaDataResultUi);
+//    ApiResult _resultInit = _honaAPI.init();
+//    ApiResult _hsruStartResult = _honaAPI.hsruStart();
+
 }
 
 MainWindow::~MainWindow()
@@ -24,56 +23,68 @@ MainWindow::~MainWindow()
 void MainWindow::honaDataResultUi(QList<HonaPacket> honaPacketList, quint32 hsruLoss, quint32 Doa)
 {
     QString _str;
-    for(auto i = 0; i < honaPacketList.length(); i++)
+    _str = QDateTime::currentDateTime().toString("hh:mm:ss.z") + "\nhonaPacketList size " + QString::number(honaPacketList.size());
+    for(auto i = 0; i < qMin(10, honaPacketList.length()); i++)
     {
-        _str += "\n[hsruLoss] :" + QString::number(hsruLoss, 16);
-        _str += "\n[getToa] :" + QString::number(honaPacketList[i].getToa(), 16);
-        _str += "\n[getDoa] :" + QString::number(honaPacketList[i].getDoa(), 16);
-        _str += "\n[getPa1] :" + QString::number(honaPacketList[i].getPa1(), 16);
-        _str += "\n[getPa2] :" + QString::number(honaPacketList[i].getPa2(), 16);
-        _str += "\n[getPa3] :" + QString::number(honaPacketList[i].getPa3(), 16);
-        _str += "\n[getPa4] :" + QString::number(honaPacketList[i].getPa4(), 16);
-        _str += "\n[getCode] :" + QString::number(honaPacketList[i].getCode(), 16);
-        _str += "\n[getCodeL] :" + QString::number(honaPacketList[i].getCodeL(), 16);
-        _str += "\n[getCodeM] :" + QString::number(honaPacketList[i].getCodeM(), 16);
+        _str += "\n[PacketType] :" + QString::number(honaPacketList[i].getPacketType());
+        _str += "\n[PacketNumber] :" + QString::number(honaPacketList[i].getPacketNumber());
+        _str += "\n[Toa] :" + QString::number(honaPacketList[i].getToa());
+        _str += "\n[Doa] :" + QString::number(honaPacketList[i].getDoa());
+        _str += "\n[Pa1] :" + QString::number(honaPacketList[i].getPa1());
+        _str += "\n[Pa2] :" + QString::number(honaPacketList[i].getPa2());
+        _str += "\n[Pa3] :" + QString::number(honaPacketList[i].getPa3());
+        _str += "\n[Pa4] :" + QString::number(honaPacketList[i].getPa4());
+        _str += "\n[Code] :" + QString::number(honaPacketList[i].getCode(), 16);
+        _str += "\n[CodeL] :" + QString::number(honaPacketList[i].getCodeL(), 16);
+        _str += "\n[CodeM] :" + QString::number(honaPacketList[i].getCodeM(), 16);
+        _str += "\n[hsruLoss] :" + QString::number(hsruLoss);
+        _str += "\n[doa] :" + QString::number(Doa);
     }
     ui->dataFromMemory->setText(_str);
+
+    qDebug() << QDateTime::currentDateTime().toString("hh:mm:ss.z") << " honaPacketList size "<< honaPacketList.size();
 }
 
-void MainWindow::on_testPLX_clicked()
+QString resultString(ApiResult res){
+
+    switch (res) {
+    case ApiResult::success:
+        return "success";
+    case ApiResult::alreadyStarted:
+        return "alreadyStarted";
+    case ApiResult::busy:
+        return "busy";
+    case ApiResult::error:
+        return "error";
+    }
+    return "";
+};
+
+
+void MainWindow::on_startHsru_clicked()
 {
+    //********************************************************
     ApiResult _resultInit = _honaAPI.init();
-    ApiResult _hsruStartResult = _honaAPI.hsruStart();
+    ui->errorMonitoring->setText("_resultInit: " + resultString(_resultInit));
 
     //********************************************************
+    ApiResult _hsruStartResult = _honaAPI.hsruStart();
     QString temp = ui->errorMonitoring->text();
-    if(_resultInit == ApiResult::error)
-    {
-        ui->errorMonitoring->setText(temp + "\n" + " Error _resultInit");
-    }
-    else if(_resultInit == ApiResult::success)
-    {
-        ui->errorMonitoring->setText(temp + "\n" + "success _resultInit");
-    }
-    //********************************************************
+    ui->errorMonitoring->setText(temp + "\n _hsruStartResult: " + resultString(_hsruStartResult));
 
-    if(_hsruStartResult == ApiResult::error)
-    {
-        ui->errorMonitoring->setText(temp + "\n" + " Error _hsruStartResult");
-    }
-    else if(_hsruStartResult == ApiResult::success)
-    {
-        ui->errorMonitoring->setText(temp + "\n" + " success _hsruStartResult");
-    }
-    //********************************************************
+}
+
+void MainWindow::on_resetDevice_clicked()
+{
+
+    ApiResult _hsruStop = _honaAPI.deviceReset();
+    ui->errorMonitoring->setText("deviceReset: " + resultString(_hsruStop));
 }
 
 void MainWindow::on_stopHsru_clicked()
 {
-    QString temp = ui->errorMonitoring->text();
+
     ApiResult _hsruStop = _honaAPI.hsruStop();
-    if(_hsruStop == ApiResult::error)
-    {
-        ui->errorMonitoring->setText(temp + "\n" + " success _hsruStartResult");
-    }
+    ui->errorMonitoring->setText("hsruStop: " + resultString(_hsruStop));
+
 }
diff --git a/Test/MainWindow.h b/Test/MainWindow.h
index 363b537..add5b8d 100755
--- a/Test/MainWindow.h
+++ b/Test/MainWindow.h
@@ -28,7 +28,8 @@ public:
     //uncrustify off
 private	slots:
     void honaDataResultUi(QList<HonaPacket> honaPacketList, quint32 hsruLoss, quint32 Doa);
-    void on_testPLX_clicked();
+    void on_startHsru_clicked();
+    void on_resetDevice_clicked();
     void on_stopHsru_clicked();
     //uncrustify on:
 
diff --git a/Test/MainWindow.ui b/Test/MainWindow.ui
index 3c00688..3e25f38 100755
--- a/Test/MainWindow.ui
+++ b/Test/MainWindow.ui
@@ -14,74 +14,53 @@
    <string>MainWindow</string>
   </property>
   <widget class="QWidget" name="centralwidget">
-   <widget class="QPushButton" name="testPLX">
-    <property name="geometry">
-     <rect>
-      <x>250</x>
-      <y>40</y>
-      <width>89</width>
-      <height>25</height>
-     </rect>
-    </property>
-    <property name="text">
-     <string>Test PLX</string>
-    </property>
-   </widget>
-   <widget class="QLabel" name="label">
-    <property name="geometry">
-     <rect>
-      <x>60</x>
-      <y>30</y>
-      <width>171</width>
-      <height>51</height>
-     </rect>
-    </property>
-    <property name="text">
-     <string>&lt;html&gt;&lt;head/&gt;&lt;body&gt;&lt;p align=&quot;center&quot;&gt;&lt;span style=&quot; font-size:20pt;&quot;&gt;Test PLX&lt;/span&gt;&lt;/p&gt;&lt;/body&gt;&lt;/html&gt;</string>
-    </property>
-   </widget>
-   <widget class="QLabel" name="errorMonitoring">
-    <property name="geometry">
-     <rect>
-      <x>50</x>
-      <y>90</y>
-      <width>411</width>
-      <height>61</height>
-     </rect>
-    </property>
-    <property name="text">
-     <string>TextLabel</string>
-    </property>
-   </widget>
-   <widget class="QPushButton" name="stopHsru">
-    <property name="geometry">
-     <rect>
-      <x>390</x>
-      <y>40</y>
-      <width>89</width>
-      <height>25</height>
-     </rect>
-    </property>
-    <property name="text">
-     <string>stopHsru</string>
-    </property>
-   </widget>
-   <widget class="QTextEdit" name="dataFromMemory">
-    <property name="geometry">
-     <rect>
-      <x>50</x>
-      <y>140</y>
-      <width>451</width>
-      <height>301</height>
-     </rect>
-    </property>
-    <property name="verticalScrollBarPolicy">
-     <enum>Qt::ScrollBarAlwaysOn</enum>
-    </property>
-    <property name="sizeAdjustPolicy">
-     <enum>QAbstractScrollArea::AdjustToContentsOnFirstShow</enum>
-    </property>
-   </widget>
+   <layout class="QGridLayout" name="gridLayout">
+    <item row="2" column="2">
+     <widget class="QPushButton" name="resetDevice">
+      <property name="text">
+       <string>resetDevice</string>
+      </property>
+     </widget>
+    </item>
+    <item row="5" column="0" colspan="3">
+     <widget class="QTextEdit" name="dataFromMemory">
+      <property name="verticalScrollBarPolicy">
+       <enum>Qt::ScrollBarAlwaysOn</enum>
+      </property>
+      <property name="sizeAdjustPolicy">
+       <enum>QAbstractScrollArea::AdjustToContentsOnFirstShow</enum>
+      </property>
+     </widget>
+    </item>
+    <item row="0" column="0">
+     <widget class="QLabel" name="label">
+      <property name="text">
+       <string>&lt;html&gt;&lt;head/&gt;&lt;body&gt;&lt;p align=&quot;center&quot;&gt;&lt;span style=&quot; font-size:20pt;&quot;&gt;Test PLX&lt;/span&gt;&lt;/p&gt;&lt;/body&gt;&lt;/html&gt;</string>
+      </property>
+     </widget>
+    </item>
+    <item row="3" column="2">
+     <widget class="QPushButton" name="startHsru">
+      <property name="text">
+       <string>startHsru</string>
+      </property>
+     </widget>
+    </item>
+    <item row="1" column="0" rowspan="3" colspan="2">
+     <widget class="QLabel" name="errorMonitoring">
+      <property name="text">
+       <string>TextLabel</string>
+      </property>
+     </widget>
+    </item>
+    <item row="4" column="2">
+     <widget class="QPushButton" name="stopHsru">
+      <property name="text">
+       <string>stopHsru</string>
+      </property>
+     </widget>
+    </item>
+   </layout>
   </widget>
   <widget class="QMenuBar" name="menubar">
    <property name="geometry">
diff --git a/Test/Test.pro b/Test/Test.pro
index 432718d..5cc32ed 100755
--- a/Test/Test.pro
+++ b/Test/Test.pro
@@ -36,13 +36,13 @@ else: unix:!android: target.path = /opt/$${TARGET}/bin
 !isEmpty(target.path): INSTALLS += target
 
 
-unix:!macx: LIBS += -L$$PWD/../../Plxlibrary/Library/ -lPlxApi
+unix:!macx: LIBS += -L$$PWD/../Plxlibrary/Library/ -lPlxApi
 
-INCLUDEPATH += $$PWD/../../Plxlibrary/Library
-DEPENDPATH += $$PWD/../../Plxlibrary/Library
+INCLUDEPATH += $$PWD/../Plxlibrary/Library
+DEPENDPATH += $$PWD/../Plxlibrary/Library
 
-INCLUDEPATH += $$PWD/../../Plxlibrary
-DEPENDPATH += $$PWD/../../Plxlibrary
+INCLUDEPATH += $$PWD/../Plxlibrary
+DEPENDPATH += $$PWD/../Plxlibrary
 
-unix:!macx: PRE_TARGETDEPS += $$PWD/../../Plxlibrary/Library/libPlxApi.a
+unix:!macx: PRE_TARGETDEPS += $$PWD/../Plxlibrary/Library/libPlxApi.a