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346 lines
16 KiB
346 lines
16 KiB
3 years ago
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#ifndef __PCI_REGS_H
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#define __PCI_REGS_H
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/*******************************************************************************
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* Copyright 2013-2020 Broadcom, Inc.
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* Copyright (c) 2009 to 2012 PLX Technology Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directorY of this source tree, or the
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* BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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******************************************************************************/
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/******************************************************************************
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*
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* File Name:
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*
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* PciRegs.h
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*
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* Description:
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*
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* This file defines the generic PCI Configuration Registers
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*
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* Revision:
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*
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* 01-01-20 : PCI/PCIe SDK v8.10
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*
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******************************************************************************/
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// PCI location max counts
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#define PCI_MAX_BUS 256 // Max PCI Buses
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#define PCI_MAX_DEV 32 // Max PCI Slots
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#define PCI_MAX_FUNC 8 // Max PCI Functions
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// PCI config space sizes
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#define PCI_CONFIG_SPACE_SIZE 0x100 // PCI = 256B
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#define PCIE_CONFIG_SPACE_SIZE 0x1000 // PCIe = 4K
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// PCI register read error values return to software
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#define PCI_CFG_RD_ERR_VAL_8 ((U8)-1)
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#define PCI_CFG_RD_ERR_VAL_16 ((U16)-1)
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#define PCI_CFG_RD_ERR_VAL_32 ((U32)-1)
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#define PCI_CFG_RD_ERR_VAL PCI_CFG_RD_ERR_VAL_32
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// Special values returned for ID read if CRS SW visibility enabled
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#define PCIE_CFG_RD_CRS_VAL_16 (U16)0x0001
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#define PCIE_CFG_RD_CRS_VAL_32 (U32)0xFFFF0001
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// PCI Header types
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#define PCI_HDR_TYPE_0 0 // Endpoint
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#define PCI_HDR_TYPE_1 1 // PCI-to-PCI bridge
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#define PCI_HDR_TYPE_2 2 // Cardbus
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#define PCI_NUM_BARS_TYPE_00 6 // Type 0 total PCI BARs
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#define PCI_NUM_BARS_TYPE_01 2 // Type 1 total PCI BARs
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// Standard PCI registers
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#define PCI_REG_DEV_VEN_ID 0x00
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#define PCI_REG_CMD_STAT 0x04
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#define PCI_REG_CLASS_REV 0x08
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#define PCI_REG_HDR_CACHE_LN 0x0C
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#define PCI_REG_BAR_0 0x10
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#define PCI_REG_BAR_1 0x14
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#define PCI_REG_CAP_PTR 0x34
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#define PCI_REG_INT_PIN_LN 0x3C
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// Type 0 specific standard registers
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#define PCI_REG_T0_BAR_2 0x18
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#define PCI_REG_T0_BAR_3 0x1C
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#define PCI_REG_T0_BAR_4 0x20
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#define PCI_REG_T0_BAR_5 0x24
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#define PCI_REG_TO_CARDBUS_PTR 0x28
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#define PCI_REG_TO_SUBSYS_ID 0x2C
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#define PCI_REG_TO_EXP_ROM 0x30
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#define PCI_REG_TO_RSVD_38H 0x38
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// Type 1 specific standard registers
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#define PCI_REG_T1_PRIM_SEC_BUS 0x18
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#define PCI_REG_T1_IO_BASE_LIM 0x1C
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#define PCI_REG_T1_MEM_BASE_LIM 0x20
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#define PCI_REG_T1_PF_MEM_BASE_LIM 0x24
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#define PCI_REG_T1_PF_MEM_BASE_HIGH 0x28
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#define PCI_REG_T1_PF_MEM_LIM_HIGH 0x2C
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#define PCI_REG_T1_IO_BASE_LIM_HIGH 0x30
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#define PCI_REG_T1_EXP_ROM 0x38
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// PCIe 1st capability pointer
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#define PCIE_REG_CAP_PTR 0x100
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// PCI Extended Capability IDs
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#define PCI_CAP_ID_NULL 0x00
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#define PCI_CAP_ID_POWER_MAN 0x01
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#define PCI_CAP_ID_AGP 0x02
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#define PCI_CAP_ID_VPD 0x03
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#define PCI_CAP_ID_SLOT_ID 0x04
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#define PCI_CAP_ID_MSI 0x05
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#define PCI_CAP_ID_HOT_SWAP 0x06
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#define PCI_CAP_ID_PCIX 0x07
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#define PCI_CAP_ID_HYPER_TRANSPORT 0x08
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#define PCI_CAP_ID_VENDOR_SPECIFIC 0x09
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#define PCI_CAP_ID_DEBUG_PORT 0x0A
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#define PCI_CAP_ID_RESOURCE_CTRL 0x0B
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#define PCI_CAP_ID_HOT_PLUG 0x0C
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#define PCI_CAP_ID_BRIDGE_SUB_ID 0x0D
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#define PCI_CAP_ID_AGP_8X 0x0E
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#define PCI_CAP_ID_SECURE_DEVICE 0x0F
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#define PCI_CAP_ID_PCI_EXPRESS 0x10
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#define PCI_CAP_ID_MSI_X 0x11
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#define PCI_CAP_ID_SATA 0x12
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#define PCI_CAP_ID_ADV_FEATURES 0x13
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#define PCI_CAP_ID_ENHANCED_ALLOCATION 0x14
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#define PCI_CAP_ID_FLATTENING_PORTAL_BRIDGE 0x15
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// PCI Express Extended Capability IDs
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#define PCIE_CAP_ID_NULL 0x000 // Empty capability
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#define PCIE_CAP_ID_ADV_ERROR_REPORTING 0x001 // Advanced Error Reporting (AER)
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#define PCIE_CAP_ID_VIRTUAL_CHANNEL 0x002 // Virtual Channel (VC)
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#define PCIE_CAP_ID_DEV_SERIAL_NUMBER 0x003 // Device Serial Number
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#define PCIE_CAP_ID_POWER_BUDGETING 0x004 // Power Budgeting
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#define PCIE_CAP_ID_RC_LINK_DECLARATION 0x005 // Root Complex Link Declaration
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#define PCIE_CAP_ID_RC_INT_LINK_CONTROL 0x006 // Root Complex Internal Link Control
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#define PCIE_CAP_ID_RC_EVENT_COLLECTOR 0x007 // Root Complex Event Collector Endpoint Association
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#define PCIE_CAP_ID_MF_VIRTUAL_CHANNEL 0x008 // Multi-Function Virtual Channel (MFVC)
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#define PCIE_CAP_ID_VC_WITH_MULTI_FN 0x009 // Virtual Channel with Multi-Function
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#define PCIE_CAP_ID_RC_REG_BLOCK 0x00A // Root Complex Register Block (RCRB)
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#define PCIE_CAP_ID_VENDOR_SPECIFIC 0x00B // Vendor-specific (VSEC)
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#define PCIE_CAP_ID_CONFIG_ACCESS_CORR 0x00C // Configuration Access Correlation
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#define PCIE_CAP_ID_ACCESS_CTRL_SERVICES 0x00D // Access Control Services (ACS)
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#define PCIE_CAP_ID_ALT_ROUTE_ID_INTERPRET 0x00E // Alternate Routing-ID Interpretation (ARI)
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#define PCIE_CAP_ID_ADDR_TRANS_SERVICES 0x00F // Address Translation Services (ATS)
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#define PCIE_CAP_ID_SR_IOV 0x010 // SR-IOV
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#define PCIE_CAP_ID_MR_IOV 0x011 // MR-IOV
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#define PCIE_CAP_ID_MULTICAST 0x012 // Multicast
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#define PCIE_CAP_ID_PAGE_REQUEST 0x013 // Page Request Interface (PRI)
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#define PCIE_CAP_ID_AMD_RESERVED 0x014 // Reserved for AMD
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#define PCIE_CAP_ID_RESIZABLE_BAR 0x015 // Resizable BAR
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#define PCIE_CAP_ID_DYNAMIC_POWER_ALLOC 0x016 // Dynamic Power Allocation (DPA)
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#define PCIE_CAP_ID_TLP_PROCESSING_HINT 0x017 // TLP Processing Hints (TPH)
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#define PCIE_CAP_ID_LATENCY_TOLERANCE_REPORT 0x018 // Latency Tolerance Reporting (LTR)
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#define PCIE_CAP_ID_SECONDARY_PCI_EXPRESS 0x019 // Secondary PCI Express
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#define PCIE_CAP_ID_PROTOCOL_MULTIPLEX 0x01A // Protocol Multiplexing (PMUX)
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#define PCIE_CAP_ID_PROCESS_ADDR_SPACE_ID 0x01B // Process Address Space ID (PASID)
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#define PCIE_CAP_ID_LTWT_NOTIF_REQUESTER 0x01C // Lightweight Notification Requester (LNR)
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#define PCIE_CAP_ID_DS_PORT_CONTAINMENT 0x01D // Downstream Port Containment (DPC)
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#define PCIE_CAP_ID_L1_PM_SUBSTRATES 0x01E // L1 Power Management Substrates (L1PM)
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#define PCIE_CAP_ID_PRECISION_TIME_MEAS 0x01F // Precision Time Measurement (PTM)
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#define PCIE_CAP_ID_PCIE_OVER_M_PHY 0x020 // PCIe over M-PHY (M-PCIe)
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#define PCIE_CAP_ID_FRS_QUEUEING 0x021 // FRS Queueing
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#define PCIE_CAP_ID_READINESS_TIME_REPORTING 0x022 // Readiness Time Reporting
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#define PCIE_CAP_ID_DESIGNATED_VEND_SPECIFIC 0x023 // Designated vendor-specific
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#define PCIE_CAP_ID_VF_RESIZABLE_BAR 0x024 // VF resizable BAR
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#define PCIE_CAP_ID_DATA_LINK_FEATURE 0x025 // Data Link Feature
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#define PCIE_CAP_ID_PHYS_LAYER_16GT 0x026 // Physical Layer 16 GT/s
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#define PCIE_CAP_ID_PHYS_LAYER_16GT_MARGINING 0x027 // Physical Layer 16 GT/s Margining
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#define PCIE_CAP_ID_HIERARCHY_ID 0x028 // Hierarchy ID
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#define PCIE_CAP_ID_NATIVE_PCIE_ENCL_MGMT 0x029 // Native PCIe Enclosure Management (NPEM)
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#define PCIE_CAP_ID_PHYS_LAYER_32GT 0x02A // Physical Layer 32 GT/s
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#define PCIE_CAP_ID_ALTERNATE_PROTOCOL 0x02B // Alternate Protocol
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#define PCIE_CAP_ID_SYS_FW_INTERMEDIARY 0x02C // System Firmware Intermediary (SFI)
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// Convert encoding of MPS/MRR to bytes (128 * (2 ^ encoded_val))
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#define PCIE_MPS_MRR_TO_BYTES(val) ( 128 * (1 << (val)) )
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// PCI device Power Management states (PM Cntrl/Stat [1:0])
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#define PCI_CAP_PM_STATE_D0 0x00
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#define PCI_CAP_PM_STATE_D1 0x01
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#define PCI_CAP_PM_STATE_D2 0x02
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#define PCI_CAP_PM_STATE_D3_HOT 0x03
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// Function codes for PCI BIOS operations
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#define PCI_FUNC_ID 0xb1
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#define PCI_FUNC_BIOS_PRESENT 0x01
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#define PCI_FUNC_FIND_PCI_DEVICE 0x02
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#define PCI_FUNC_FIND_PCI_CLASS_CODE 0x03
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#define PCI_FUNC_GENERATE_SPECIAL_CYC 0x06
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#define PCI_FUNC_READ_CONFIG_BYTE 0x08
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#define PCI_FUNC_READ_CONFIG_WORD 0x09
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#define PCI_FUNC_READ_CONFIG_DWORD 0x0a
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#define PCI_FUNC_WRITE_CONFIG_BYTE 0x0b
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#define PCI_FUNC_WRITE_CONFIG_WORD 0x0c
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#define PCI_FUNC_WRITE_CONFIG_DWORD 0x0d
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#define PCI_FUNC_GET_IRQ_ROUTING_OPTS 0x0e
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#define PCI_FUNC_SET_PCI_HW_INT 0x0f
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// PCI SIG Vendor IDs
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#define PLX_PCI_VENDOR_ID_LSI 0x1000
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#define PLX_PCI_VENDOR_ID_PLX 0x10B5
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#define PLX_PCI_VENDOR_ID_BROADCOM 0x14E4
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#define PLX_PCI_VENDOR_ID_AMD 0x1022
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#define PLX_PCI_VENDOR_ID_HEWLETT_PACKARD 0x103C
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#define PLX_PCI_VENDOR_ID_HP_ENTERPRISE 0x1590
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#define PLX_PCI_VENDOR_ID_HITACHI 0x1054
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#define PLX_PCI_VENDOR_ID_HUAWEI 0x19E5
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#define PLX_PCI_VENDOR_ID_IBM 0x1014
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#define PLX_PCI_VENDOR_ID_INTEL 0x8086
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#define PLX_PCI_VENDOR_ID_LENOVO 0x1D49
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#define PLX_PCI_VENDOR_ID_MARVELL 0x1148
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#define PLX_PCI_VENDOR_ID_MATROX 0x102B
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#define PLX_PCI_VENDOR_ID_MELLANOX 0x15B3
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#define PLX_PCI_VENDOR_ID_NETAPP 0x1275
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#define PLX_PCI_VENDOR_ID_NVIDIA 0x10DE
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#define PLX_PCI_VENDOR_ID_QUALCOMM 0x5143
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#define PLX_PCI_VENDOR_ID_REALTEK 0x10EC
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#define PLX_PCI_VENDOR_ID_SAMSUNG 0x144D
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#define PLX_PCI_VENDOR_ID_SEAGATE 0x1BB1
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#define PLX_PCI_VENDOR_ID_TOSHIBA 0x1179
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#define PLX_PCI_VENDOR_ID_WESTERN_DIGITAL 0x1B96
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// PCIe ReqID support macros
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#define PCIE_REQID_BUILD(bus,dev,fn) (((U16)(bus) << 8) | ((dev) << 3) | ((fn) << 0))
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#define PCIE_REQID_BUS(ReqId) ((U8)((ReqId) >> 8) & 0xFF)
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#define PCIE_REQID_DEV(ReqId) ((U8)((ReqId) >> 3) & 0x1F)
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#define PCIE_REQID_FN(ReqId) ((U8)((ReqId) >> 0) & 0x7)
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// PCIe TLP format
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typedef enum _PCIE_TLP_FORMAT
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{
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PCIE_TLP_FORMAT_3DW_NO_DATA = 0x0,
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PCIE_TLP_FORMAT_4DW_NO_DATA = 0x1,
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PCIE_TLP_FORMAT_3DW_DATA = 0x2,
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PCIE_TLP_FORMAT_4DW_DATA = 0x3,
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PCIE_TLP_FORMAT_TLP_PREFIX = 0x4
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} PCIE_TLP_FORMAT;
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// PCIe TLP Types
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typedef enum _PCIE_TLP_TYPE
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{
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TLP_TYPE_MEM_READ_32 = 0x00,
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TLP_TYPE_MEM_READ_64 = 0x20,
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TLP_TYPE_MEM_READ_LOCK_32 = 0x01,
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TLP_TYPE_MEM_READ_LOCK_64 = 0x21,
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TLP_TYPE_MEM_WRITE_32 = 0x40,
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TLP_TYPE_MEM_WRITE_64 = 0x60,
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TLP_TYPE_IO_READ = 0x02,
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TLP_TYPE_IO_WRITE = 0x42,
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TLP_TYPE_CFG_READ_TYPE_0 = 0x04,
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TLP_TYPE_CFG_WRITE_TYPE_0 = 0x44,
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TLP_TYPE_CFG_READ_TYPE_1 = 0x05,
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TLP_TYPE_CFG_WRITE_TYPE_1 = 0x45,
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TLP_TYPE_MSG_TO_RC = 0x30,
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TLP_TYPE_MSG_BY_ADDRESS = 0x31,
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TLP_TYPE_MSG_BY_ID = 0x32,
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TLP_TYPE_MSG_RC_BROADCAST = 0x33,
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TLP_TYPE_MSG_TO_RECEIVER = 0x34,
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TLP_TYPE_MSG_GATHERED_TO_RC = 0x35,
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TLP_TYPE_MSGD_TO_RC = 0x70,
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TLP_TYPE_MSGD_BY_ADDRESS = 0x71,
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TLP_TYPE_MSGD_BY_ID = 0x72,
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TLP_TYPE_MSGD_RC_BROADCAST = 0x73,
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TLP_TYPE_MSGD_TO_RECEIVER = 0x74,
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TLP_TYPE_MSGD_GATHERED_TO_RC = 0x75,
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TLP_TYPE_CPL_NO_DATA = 0x0A,
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TLP_TYPE_CPL_WITH_DATA = 0x4A,
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TLP_TYPE_CPL_LOCKED_NO_DATA = 0x0B,
|
||
|
|
TLP_TYPE_CPL_LOCKED_WITH_DATA = 0x4B,
|
||
|
|
TLP_TYPE_FINAL_ENTRY = 0xFF // Must be last entry
|
||
|
|
} PCIE_TLP_TYPE;
|
||
|
|
|
||
|
|
|
||
|
|
// PCIe Completion TLP status
|
||
|
|
typedef enum _PCIE_TLP_CPL_STATUS
|
||
|
|
{
|
||
|
|
TLP_CPL_STATUS_SUCCESS = 0x00,
|
||
|
|
TLP_CPL_STATUS_UNSUPP_REQ = 0x01,
|
||
|
|
TLP_CPL_STATUS_CONFIG_RETRY = 0x02,
|
||
|
|
TLP_CPL_STATUS_COMPLETER_ABORT = 0x04
|
||
|
|
} PCIE_TLP_CPL_STATUS;
|
||
|
|
|
||
|
|
|
||
|
|
// PCIe Message TLP routing
|
||
|
|
typedef enum _PCIE_TLP_MSG_ROUTE
|
||
|
|
{
|
||
|
|
TLP_MSG_ROUTE_TO_RC = 0x00,
|
||
|
|
TLP_MSG_ROUTE_BY_ADDR = 0x01,
|
||
|
|
TLP_MSG_ROUTE_BY_ID = 0x02,
|
||
|
|
TLP_MSG_ROUTE_RC_BROADCAST = 0x03,
|
||
|
|
TLP_MSG_ROUTE_LOCAL_TERMINATE = 0x04,
|
||
|
|
TLP_MSG_ROUTE_GATHERED_TO_RC = 0x05,
|
||
|
|
} PCIE_TLP_MSG_ROUTE;
|
||
|
|
|
||
|
|
|
||
|
|
// PCIe Message TLP types
|
||
|
|
typedef enum _PCIE_TLP_MSG
|
||
|
|
{
|
||
|
|
TLP_MSG_UNLOCK = 0x00,
|
||
|
|
TLP_MSG_LATENCY_TOLERANCE_REP = 0x10,
|
||
|
|
TLP_MSG_OPT_BUFF_FLUSH_FILL = 0x12,
|
||
|
|
TLP_MSG_PM_ACTIVE_STATE_NAK = 0x14,
|
||
|
|
TLP_MSG_PM_PME = 0x18,
|
||
|
|
TLP_MSG_PM_PME_TURN_OFF = 0x19,
|
||
|
|
TLP_MSG_PM_PME_TO_ACK = 0x1B,
|
||
|
|
TLP_MSG_ERROR_CORRECTABLE = 0x30,
|
||
|
|
TLP_MSG_ERROR_NON_FATAL = 0x31,
|
||
|
|
TLP_MSG_ERROR_FATAL = 0x33,
|
||
|
|
TLP_MSG_ASSERT_INTA = 0x20,
|
||
|
|
TLP_MSG_ASSERT_INTB = 0x21,
|
||
|
|
TLP_MSG_ASSERT_INTC = 0x22,
|
||
|
|
TLP_MSG_ASSERT_INTD = 0x23,
|
||
|
|
TLP_MSG_DEASSERT_INTA = 0x24,
|
||
|
|
TLP_MSG_DEASSERT_INTB = 0x25,
|
||
|
|
TLP_MSG_DEASSERT_INTC = 0x26,
|
||
|
|
TLP_MSG_DEASSERT_INTD = 0x27,
|
||
|
|
TLP_MSG_SET_SLOT_POWER_LIMIT = 0x50,
|
||
|
|
TLP_MSG_VENDOR_DEFINED_TYPE_0 = 0x7E,
|
||
|
|
TLP_MSG_VENDOR_DEFINED_TYPE_1 = 0x7F,
|
||
|
|
TLP_MSG_FINAL_ENTRY = 0xFF // Must be last entry
|
||
|
|
} PCIE_TLP_MSG;
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|